Vaire co-founders discuss adiabatic reversible computing

Interviews | July 12, 2024

By Peter Clarke

Reversible computing

eeNews Europe asked Rodolfo Rosini and Hannah Earley, co-founders of Vaire Computing Ltd., to discuss reversible computing, which is the technical basis of their startup.

Rosini, who serves as CEO of the company, is a serial entrepreneur who has founded companies in AI, gaming and cellphone security. “I decided that developing and introducing a CPU architecture must be one of the most complex tasks in the world; one of the hardest things you can do. I wanted to try,” Rosini told eeNews Europe.

Earley gained a PhD from University of Cambridge before co-founding Vaire Computing in 2021 and taking the position of CTO. At Cambridge her research interests include reversible computing and molecular programming and she states she is now moving towards the practical implementation of some of these ideas (see Startup Vaire says first reversible computing chip due in a year).

Reversible computing is fundamentally different to the “classical” computing that underlies nearly all the commercial computation deployed to date, although the topic has been the subject of academic research since the 1960s.

Near-zero energy

Vaire’s goal is to produce an AI processor or accelerator that is approaching 4,000 times more energy efficient than similar devices implemented classically.

“What we can do is make near-zero-energy chips. Our flavour is adiabatic reversible computing. We can operate at room temperature and dissipate almost no power,” said Rosini. Earley added: “We are doing this in digital CMOS. The approach is to manage how logic is laid out at the gate level and the speed at which transitions occur.”

Adding reversibility to a computation process means that inputs are not lost on the creation of an output. It has been shown in academic research that it is only the destruction of information that sets a fundamental energy limit – the Landauer limit – on computation. Reversible computing would allow that limit to be transcended.

The adiabatic part of the approach is the prevention of the consumption of energy by the movement of charge, through the use of resonant structures. In other words, the work done in classical computing gets turned into heat by dumping charge to ground. If that energy can be recovered within the system it can be reused for subsequent operations. This together with the reversibility allows for theoretical energy efficiency gains in complex systems of more than three orders of magnitude, according to academic publications.

These are bold claims that have been pursued by a few startups (see Metis emerges with ‘data-is-energy’ IP).

Transition slowly

One of the ways to minimize energy consumption is to allow bit transitions take place slowly. Classical computing, even at gigahertz clock frequencies, has rapid bit transitions driven by nearly square wave clock signals which results in high resistance and losses through heating. There are then ‘long’ waits for the next clock edge. By using trapezoidal waveforms with gentle gradients and by allowing transitions to occupy a greater proportion of a clock period, charge can flow in and out of resonant structures in an adiabatic, or near-adiabatic manner. One of the ways to manage this is by the use of multiple clocks to control the rise and fall of signals.

If transitions were infinitely slow the switching operation would dissipate no energy – and produce no heat – except for that due to leakage currents. Fortunately, the major part of this benefit is seen relatively quickly meaning that close to conventional clock rates should still be possible, Earley explained.

Earley said that Vaire is using neither a single-rail nor a dual-rail (signal and inverse) logic system. “So, the exact rail system is neither, but the specifics are not yet public. I can say though that single-rail is generally not ideal in reversible computing systems. And yes, we require more clocks than classical CMOS. But our approach requires far fewer clocks than some logic families that have come in the past such as SCRL – 24 or more – or Bennett clocking – arbitrarily many.”

The complexities of multiple signal rails and multiple clocks are some of the reasons adiabatic reversible computing has not been adopted in the mainstream; the theoretical benefits come with many overheads and trade-offs. In addition, there is the chicken-and-egg problem of a lack of foundry and EDA software support.

As long as Moore’s Law was helping drive performance and to a lesser extent energy efficiency there was insufficient incentive to jump to reversible computing, Rosini said. However, with the rising awareness of the sustainability challenges around artificial intelligence Rosini reckons reversible computing’s time has come. “AI is reaching the point where suddenly changing to a different paradigm is not only worthwhile but it is becoming essential,” he said.

Underlining the point Earley said: “We are looking to be 4,000x more energy efficient than classical computing.” Rosini added: “For 50 years we’ve had classical computing that was irreversible. I believe we are crossing a threshold to where everything will be reversible.”

Earley added that quantum computing is one of the purest forms of reversible computing and that reversible photonic computation may be adopted eventually for reasons of power efficiency.

Alternative gates

However, reversability requires a 1-to-1 correlation between inputs and outputs which therefore also requires different types of logic gates internally. For example, the operation of a two-input, one-output NAND gate is destructive of input information and so alternative gate structures and architectures have to be found.

“One-to-one equivalence is not a limitation although it does require consideration,” said Earley. “We thought it might require a new instruction set architecture, different fundamental libraries,” she added. “We have done a lot of work to develop and optimize our standard cell library and how these cells can be combined into different logical functions.”

Rosini added: “But we can isolate any differences within the chip. So, from the outside it looks like a conventional software target. We don’t want to throw away the [software] infrastructure. It is still deterministic computing.”

Vaire recently announced that it was intended to have a reversible computing chip out within 12 months (see Startup Vaire says first reversible computing chip due in a year).

Earley confirmed the company’s first tape out is being designed for a 22nm manufacturing process, but declined to name the foundry or the manufacturing process Vaire is targeting. The key choice here would be between planar, FinFET or fully-depleted silicon-on-insulator processes. Earley said that Vaire’s adiabatic reversible logic is essentially process agnostic. “We’ve conducted CAD simulations at many levels of abstraction,” said Earley. “What we need to do is validate we can recycle charge at the levels we expect.”

This first tape-out is planned to be one of series of test chips that will progress from gates and simple functions such as adders including resonant structures, up to functional blocks, and culminating in a software-programmable circuit.

Resonant structures?

So, what are those resonant structures? Passive LCR circuits would probably be the easiest to integrate but do they provide the performance and control required? Would active, transistor-based circuitry perform better – but at what cost? And what about MEMS?

Earley declined to provide details. “We are investigating many resonator options, as they each have trade-offs that make sense for different product segments. The difficulty with MEMS is that the development process is a lot less standardized and requires deeper manufacturing expertise than mixed-signal CMOS, and so timelines for prototyping MEMS-based resonators are longer.”

Vaire is also looking at the higher levels of the hardware-software stack. Rosini said work on compilation is underway and that Andrew Sloss, vice president of technology at Vaire Computing, had previously been responsible for a reversible computing research program at processor licensor Arm Ltd. (see Arm engineering veteran joins ‘reversible computing’ startup). Vaire has also recruited Mike Frank, a prominent researcher in the field of reversible computing at Sandia National Laboratories, as a senior scientist.

Rosini is very clear that he wants to create a fabless chip company with a processing product offering under its own brand. The alternative way forward – of creating functional IP and licensing that to chip companies – does not capture enough of the value created Rosini said. “We’ve already had companies asking about licensing and politely declined,” he added.

But the product business model will require considerably more funding for the company to progress up through the generations of test-chips. Rosini said that he expects Vaire to have a product in the market in 2027.

But can Vaire achieve superiority in terms of performance, energy efficiency and cost, given the additional circuitry, more complex gates and resonant structures required? This is the so-called PPA – performance, power, area – trade off.

Volumetric computing

Earley said that chasing advantage in a single planar circuit is not what Vaire’s architecture is going to be about. “The performance benefits really come when we pursue multi-layered, volumetric computing,” she said. That’s because Vaire’s energy efficiency will allow circuits to be stacked densely, whereas classical processing circuits cannot do the same, due to thermal considerations.

Earley said that for simple serial computation, especially with strong data dependencies, reversible computing is likely to show little or no benefit over classical computing. “Whilst it IS general purpose, adiabatic reversible logic is far better suited to highly parallel operations,” she said.

And that describes the AI sector where energy consumption is becoming a serious challenge. AI is also a sector where Rosini has already done business. “We want to enter with a generic NPU [neural processing unit] chip for the edge,” he said.

Fortunately, Vaire does not necessarily have to create an entire processing system. The easiest point of introduction for adiabatic reversible logic could be within a hybrid architecture.

Earley said: “Our most recently filed patent is, in fact, on exactly this – hybrid irreversible-reversible systems. There are diminishing returns to reversibilizing everything – though these returns do improve as one gets better on the energy recovery side. This is a large part of our roadmap, starting with a chip where the largest energy sinks have been converted to use reversible logic, and then increasing reversible functionality and complexity over time as it makes sense.”

Questions remain regarding the introduction of adiabatic reversible computing. Will it have its own ISA or be spliced to an Arm or RISC-V processor in a hybrid implementation? How are active memories implemented and how are they interfaced to non-volatile memory? And much will hinge on the benchmarking of those first prototype chips.

Radical technology change is difficult to achieve in the chip industry but the increasing use and power consumption of AI applications in the datacenter and the need to be frugal with power to perform AI at the edge could make adiabatic reversible computing something that eventually resonates with customers.