Vaire tips ‘reversible computing’ circuit that recycles 50% of energy
Vaire Computing Ltd. (London, England) has said it is awaiting the delivery of its first physical test chip as part of its attempt to develop reversible computing and is expecting to see 50 percent energy recycling.
The circuit is a resonator. Vaire claims that computer-based simulations show savings of 50 percent should be achieved. Resonator circuits are used in digital logic for clock signal generation, frequency stablization and frequency synthesis.
As the name suggests, reversible computing is a computational paradigm where every operation can be reversed – meaning the outputs of an operation can be used to reconstruct the inputs. This is in contrast to traditional computing, which loses information and therefore energy, mostly as heat. Every time reversible computing overwrites or erases data both the information and the energy is preserved, allowing the energy to be reused for further computations. It has to be remember that the clock signal also has to be made reversible as well.
This reversibility does require more complex circuits and gates than traditionally used and therefore some additional operational power but with the benefit of recycling most of the power.
In theory 100 percent energy recycling is possible. But if Vaire can show double-digit percentage power saving it will be noteworthy and is probably one of the benchmarks to be met for the company to raise more venture capital from existing investors. Vaire announced it had raised US$4.5 million in July 2024.
Vaire, founded in 2021 by serial entrepreneur Rodolfo Rosini (CEO) and Cambridge University researcher Hannah Earley (CTO), has kept its promise to produce a first reversible computing chip within a year of July 2024, albeit a relatively simple test chip. And, if this performance can meet or exceed what simulation suggests it could serve to encourage a clutch of startups pioneering novel computational architectures.
Earley told eeNews Europe in email correspondence that Vaire’s first tape-out is a full adiabatic reversible computing system, with both a resonator and logic. “However, for reasons of limited engineering resources we focused more of our effort on the resonator – the logic was intentionally kept relatively simple and unoptimized – shift registers and adders,” said Earley. “Our second tapeout is focusing substantially more on the logic and aiming to get towards not just energy recovery but competitive PPA.” PPA refers to the product of performance, power and area.
Earley added that the test chip is manufactured in a 22nm planar CMOS manufacturing process but declined to identify Vaire’s foundry supplier.
Related links and articles:
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Vaire co-founders discuss adiabatic reversible computing
Startup Vaire says first reversible computing chip due in a year
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