VC-2 Low Delay codec ready to run UHD and 4K transport on ASIC/FPGA

VC-2 Low Delay codec ready to run UHD and 4K transport on ASIC/FPGA

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By eeNews Europe

The low-footprint core is now ready to be integrated in both ASIC and FPGA designs without need for expensive footprint. This opens up new possibilities for equipment manufacturers as they get a low-cost, interoperable compression solution to upgrade video transport to high-definition formats such as UHD and 4K.

Barco Silex’ solution implements the VC-2 Low Delay codec. Originally conceived at the BBC labs, VC-2 LD is a lightweight, low-cost, patent-free solution that can either be added to the existing hardware or run in software. It compresses video 4:1 visually lossless and allows for sub-millisecond delays, which is essential for video applications that require (near) real-time operation.

Most importantly, VC-2 LD has been accepted as a standard (SMPTE 2042), which ensures equipment supplier support and interoperability. To prove its solution is ready for the AV market, the video experts from Barco Silex have now validated their ASIC/FPGA implementation against the latest available VC-2 conformance reference software. In addition, they have proven the interoperability between their implementation and the BBC’s open-source software, encoding through their IP core and decoding with the software.

Barco Silex ships its blocks, with a functional simulation test bench, synthesis and implementation scripts, and full documentation.

Visit Barco Silex at

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