Verification IP for the latest chip standards

New Products |
By Nick Flaherty

Cadence Design Systems has launched 15 Verification IP (VIP) packages for engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols in industrial, automotive, hyperscale data centre and mobile chips.

The VIP packages support standards including LPDDR5x, MIPI I3C and CSI-2 4.0 and UFS 4.0, and the newest versions of the USB4, ARM AMBA 5 CHI on chip interconnect and GDDR graphics memory interfaces.

The packages provide a comprehensive verification chain for the most complex protocols with access to a consistent API across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications.

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In automotive the VIP supports MIPI A-PHYsm 1.0, MIPI DSI-2sm 2.0, Flash ONFI 5.0 and CAN XL while data centre chip developers can use the VIP for CCIX 2.0. For consumer and mobile the VIP supports DisplayPort 2.1, Ethernet 5G, LPDDR5x, UFS 4.0 and the latest version of USB4

All Cadence VIP solutions include Cadence TripleCheck technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The packages also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers.

“STMicroelectronics has successfully utilized a broad range of Cadence VIP, including Arm AMBA, Memory Models, MIPI I3C and CSI-2, eUSB2 and the advanced Cadence System VIP solution, which enabled us to deliver industry-leading solutions for key projects, including ST Industrial MCUs and MPUs,” said Philippe d’Audigier, system-on-chip hardware design director at STMicroelectronics. “Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. We look forward to continuing our collaboration to develop our next-generation products.”

“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “By introducing these 15 new VIP, Cadence provides customers with solutions that ensure they can keep up with evolving standards. Our customers can confirm their designs comply with the standard specifications and application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”

The VIP packages are part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio and the vManager Verification Management Platform.

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