Verification of SoC internal channel characterization using an ADC

Verification of SoC internal channel characterization using an ADC

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By eeNews Europe

A generic Nyquist Data Converter-based Analog to Digital Converter (ADC), based on a Successive Approximation Register (SAR) or Redundant Signed Digit (RSD) Algorithm, is shown in the block diagram in Figure 1. Industrial convention is to call an ADC based on a SAR Algorithm as a SAR ADC; the one based on RSD Algorithm as a Cyclic ADC. In the generic architecture of such ADCs there are two switches. One is called the Sampling Capacitor Switch and the other an ADC Switch. For an ADC to convert an analog signal to its corresponding digital word there are 2 phases: Sampling Phase and Conversion Phase.
Sampling Phase

In this phase the sampling capacitor switch is closed and the ADC Switch is open, as shown in Figure 1. As is evident, the ADC Driver is connected to the sampling capacitor via the sampling capacitor switch. The potential of the ADC driver is basically the voltage that the ADC would convert to a digital word after the end of sampling and conversion phases.

During the sampling phase the voltage of the ADC driver will be sampled on the sampling capacitor depending upon the source impedance (R) of the connection between the ADC driver and sampling capacitor and the capacitance value of the sampling capacitance (C). Basically the sampling time should be 5-10 times the RC values to sample the correct voltage on the sampling capacitor. Also the profile of the potential built on the sampling capacitor depends on the current drive strength of the ADC driver.

Sampling time is generally a few clock cycles. There are a couple of ways to alter the sampling time of the ADC. The number of clock cycles may increase/decrease or the frequency of clock can be changed (within ADC clock frequency range) and thus sampling time can be changed.

Figure 1: State of the ADC switches during the sampling phase

Conversion phase

Figure 2 shows the state of the ADC in the conversion phase. In the conversion phase the ADC switch closes and the sampling capacitor switch opens. Now the ADC would convert the voltage that is sampled on the sampling capacitor. Any change in the ADC driver voltage would not be seen in the ADC output. That concept is called sample and hold. Now depending on the architecture of the ADC, the conversion would be done and it would take a few clock cycles to do so. Once the conversion is done, the ADC switch would again open and the sampling capacitor switch would again close for the ADC to sample a voltage again; this way the ADC would keep converting.

Figure 2: State of ADC switches during the conversion phase

After understanding the basic concepts of sampling and conversion time let us look at some waveforms to understand the intricacies of the design. Figure 3 shows the timing diagram of an ADC conversion cycle. As seen, the sampling time is two clock cycles and the conversion time is more than seven clock cycles.

Now let us try to analyze the voltage profile of the ADC driver in two cases: when the ADC driver has large current driving capacity (strong driver) and a case when it does not have a large current driving capacity (weak driver). At the beginning of the sampling phase, as soon as the sampling switch closes, the sampling capacitor load is seen by the ADC driver. There will be a large inrush current at that moment because of the capacitive charging action.

This instantaneous current surge might result in a drop in the voltage level of the ADC driver. As charge (current x time) is accumulated on the ADC capacitor, the current requirement by the sampling capacitor would reduce and the voltage would come back to its original level .

The time taken by the voltage to come back would depend on the current that the driver can support. If the driver is strong and it can supply large amount of current then it would eventually deposit more charge on the capacitor in lesser time and bring the potential of the sampling capacitor close to that of the ADC driver. This is seen in the waveform for the strong driver.

But when we talk about a weak driver then the current might be low and the total charge deposited on the sampling capacitor in the sampling time might be less and would eventually mean that the potential sampled at the sampling capacitor is not correct. This can be seen in the behavior of the weak driver profile. It would essentially mean that with a weak driver at the ADC channel the voltage sampled may be less and thus inaccurate results may be sampled by the ADC.

Figure 3: Strong and weak driver Voltage profile during sampling and conversion time

To overcome this issue the sampling time of the ADC must be increased. This can be achieved in two ways. Either increase the clock pulses in the sampling time or decrease the frequency of operation of the ADC. Many ADC architectures might not support a feature of multiple sampling times so we may need to work with low frequency when trying to convert the analog voltage of a weak driver.

This behavior can be seen in the next diagram. In this diagram we see that the sampling time of the ADC was increased by increasing the number of clock cycles to three clock cycles. Since now the ADC Driver gets almost 50% more time to accumulate the charge, even with a lower current the ADC could sample the correct amount of charge and the ADC output now would be fine.


Figure 4:  How the voltage sampled at the sampling capacitor can be corrected when supplying the ADC with a weak driver
In many SoCs it is a customer need to sample multiple signals that are internal to the SoC. Also during characterization of IPs even the designers and SoC engineers use the ADC and convert many of the IP signals that are internal to the SoC via the ADC and get crucial information about the working of the IP. It’s not only the external channels and source that the ADC samples now, it even samples multiple internal channels.

In many of the internal channels the issue of weak drivers might come. It might also happen because these signals are driven on to the ADC channel via a transmission gate which might have a varying large resistance depending on what the potential of the signal is being exposed.  Since these channels are generally driven by small buffers, they are not capable of effectively supplying a load as big as the sampling capacitor of the ADC. Therefore, it is supremely important to either increase the sampling time during conversion of such channels or make the frequency low in order to capture correct behavior of the IP from the ADC.

Therefore verification/validation/test engineers who use an ADC to characterize internal IPs like a DAC or PMC internal signals like a band-gap, the reference or various other thresholds must take care of the sampling time need and strong/weak driver profile.

About the authors

Kushal Kamal is a Senior Design Engineer.

Kamal holds a B.Tech degree from Manipal Institute of Technology, Manipal in Electrical and Electronics Engineering. Kamal has roughly 3.5 years of Industry experience and has been doing SoC Level SPICE based Analog and Mixed Signal Simulations for complex, low power mixed signal SoCs. By virtue of verifying these SoCs Kamal has gathered a basic understanding of SoC Integration, Testebench and Verification Environment. Kamal also understands the basics of IPs like PMC, ADC, Crystal Oscilltors, RC Oscillator, PLLs, LCD Controller etc. The SoCs that Kamal has been a part of are mainly from two segments: Automotive and Industrial Market. Kamal also expertise in running low power use cases in a Full Chip SPICE environment. Kamal has been one granted patent from USPTO on ADC Design and two filed patents on PMC Design and LCD Verification methodology. Kamal has also co-authored and presented two different papers on Mixed Mode Simulation Methodology and related automation that have been awarded best paper aw

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