Verification systems provider adds silicon Design for Testability analysis
asureDFT extends TVS’s expertise in test and verification into the DFT domain where ever-increasing design complexity combined with complex on-chip variation effects at lower process modes have introduced challenges for achieving first-pass silicon success. To attain desired yield levels, it is necessary to invest additional time and effort in developing custom DFT strategies. TVS’s asureDFT services suite aims to address this need by helping clients design and implement a DFT strategy that delivers improved execution, quality and reduced time-to market.
The TVS asureDFT services suite includes Scan, ATPG, Memory BIST (MBIST), Logic BIST (LBIST), JTAG, Formal Verification and ATE support. These are augmented by training support for DFT strategy/structural testing, together with training for JTAG, Scan, Boundary Scan and MBIST. TVS can also provide off-the-shelf components for JTAG TAP based test controllers, test suites for verifying BSCAN, generate tester compatible vectors for ATE and format conversions with ATE logs for diagnosis.
“asureDFT is a natural extension of TVS’s core expertise in the hardware verification domain,” said Mike Bartley, TVS founder and CEO. “TVS can deliver end-to-end DFT support – from design all the way up to silicon. For organisations looking to develop a DFT methodology, TVS can help reduce project overheads by eliminating the need to hire costly DFT resources. For organisations that already have a DFT architecture in place, TVS can provide an assessment and suggest improvements to the existing methodology.”
TVS; www.testandverification.com/solutions/structural-testing/
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