Verification update at DVCon Europe 2016: registration deadline approaching

Verification update at DVCon Europe 2016: registration deadline approaching

Technology News |
By Graham Prophet

DVCon styles itself as the foremost event for verification technologies and techniques in Europe and as such, its content is centred on the concerns of the European industry. EDN Europe spoke to Intel’s Oliver Bell, General Chair, from Intel), Infineon’s Matthias Bauer, Program Chair and NXP’s Martin Barnasconi, Past Chair to discuss the particular areas of focus of this year’ proceedings (individual remarks aren’t attributed here).


Major areas of interest include UVM, virtual prototyping – and a significant amount of added content on verification of mixed signal designs, rather than purely digital systems. In the same vein – reflecting the focus on the concerns of the European design base – there is an invreased attention to functional safety. This, unsurprisingly, is largely driven by and addresses the concerns of the automotive sector, who make up the largest single sector of the audience. Attendance, overall, has has been growing and the organisers anticipate over 300 delegates for the 2016 event. They (the organising committee) have noted a demand for training and practical guidance, and have responded by constructing this year’s agenda with a increased proportion of tutorial and “hands-on” content. Similarly, there will be no poster sessions but instead, a series of short-format presentations that are termed ‘lightning’ session, to provide a quick update on a very specific topic.


All of today’s verification ‘hot topics’ are covered. UVM gets, say the conference organisers, an emphasis on the ‘U’ (universal), looking at its expanded usage for whole-system verification. TLM, formal methods, IP verification, and a ‘special day’ examination of trends in the use of SystemC, are all scheduled for both regular-session and tutorial treatment. Virtual prototyping, in particular, gets an extended slot in the programme.


Naturally, there are sessions presented by the “EDA heavyweights”; Cadence lends its name to a tutorial on ISO 26262, which according to the session headline, “changes everything”. And Mentor’s name is to be found attached to a tutorial, “Back to Basics; Doing Formal the Right Way”. Likewise a Synopsys-sponsored tutorial is headed, “Applying UPF 3.0 for Early, System-level Power Analysis of SoCs with DDR Memories”.


High-profile Keynote presentations are scheduled to commence each day’s proceedings. On the opening day, Hobson Bullman, General Manager of the Technology Services Group at ARM, and a member of board at ARM KK, will speak on “Design and Verification Focus in ARM TSG”. TSG is ARM’s Technology Services Group; its engineering infrastructure and workflow support for compute and tooling requirements. TSG tools and services are used by ARM engineers across all regions and functions, across software, process and system design, and physical implementation. This Keynote will address some of the methodology and infrastructure challenges faced, and solutions delivered by TSG, for delivering IP across a wide variety of markets.


On the second day, the address is to be given by Juergen Weyer the Vice President of Automotive Sales for EMEA at NXP, who will speak on “The Road Ahead for the Securely Connected, Self-Driving Car”. Takin in CMOS radar, V2V and V2I communications, sensor fusion and in-car Gigabit Ethernet, this presentation will present an in-depth examination of the specific technologies driving the autonomous vehicles revolution of the future, while detailing the security, reliability and safety requirements necessary to realize its full potential.


Advanced Registration closes on Thursday 29th September 2016; the full programme and details fo the event are at;









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