Video image stabilisation IP core is optimised for Xilinx’ Zynq-7000 SoC
The IP core can be configured to be highly resource efficient and very low power if required.
While current electronic image stabilisation approaches use prominent image features to generate frame-to-frame flow vectors, and relatively simple processing in order to achieve sufficient throughput performance, RFEL’s approach is to process image frames on a tiled basis in the spatial frequency domain. This allows the IP Core to process all of the scene information and gives a far more robust and accurate stabilisation solution.
RFEL’s new Stabilisation IP Core is a high-performance video processing system that can readily support high input resolutions and frame rates, while maintaining low latency and power consumption.
The algorithm implemented within the IP core stabilises images subjected to two-dimensional translations and rotations, from both static and moving platforms. The stabilisation function provides real-time correction at frame-rates of up to 150 Hz for various imaging devices, or for resolutions of up to 1080p including both daylight and infrared cameras. For example, a 1080p colour camera operating at 8 bits and with a frame-rate of 60 Hz, necessitates operation with an input data rate of about 1 Gbits/s. The accuracy of image stabilisation, achieved when tested using a very diverse and demanding range of evaluation video data, has been shown to be better than ± 1 pixels, even when subjected to random frame-to frame displacements of up to ± 25 pixels in the x and y directions and with a frame-to-frame rotational variation of up to ± 5˚. The image stabilisation IP-core is designed to work on all suitable major FPGA vendors’ devices, although additional performance is available for Xilinx Zynq-7000 SoC devices only.
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