Virtual network co-simulation IP for 800G Ethernet
Avery Design Systems has launched fully-tested Verification IP (VIP) for 800Gbit/s Ethernet that can be used to perform virtual network co-simulation for the full layer Ethernet 2-7 network stack.
The combination of the VIP and a virtual co-simulation/co-emulation system enables the running of full hardware/software system verification on pre-silicon SoC RTL and software integrations. System designers can now perform system-level validation of an SoC design’s Ethernet and TCP/IP network interfaces using real network traffic workloads of communication, datacentre, and storage network protocols running on either host OS or virtual machine (guest OS) platforms.
The challenge is ensuring the verification IP can run at the speeds needed for 800Gbit/s Ethernet with the processing needed. The virtual platform co-simulation virtualizes host or embedded devices such as PCIe, CXL, AMBA, and now Ethernet interfaces, so verification can be performed under actual operational conditions, including verification of software integration.
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A key application for Ethernet VIP is NVMe-over-TCP which applies TCP application interfaces in pure software-only host driver or optimized hardware offload to implement disaggregated, composable block storage systems across a standard IP and Ethernet network. Alternatively, in large, distributed compute server architectures, designers can incorporate NVMe-MI in-band usage models over IP control path networks for centralized discover and control
The platform can be used to run applications such as SSH, Linux kernel SW-based IPsec/MACsec or TCP/IP client-server programs as well as custom OS drivers, SDKs, and user space programs
The virtual network device can be viewed as a simple Ethernet device, which instead of receiving packets from a physical media (Ethernet NIC), receives them from the Ethernet MAC/PHY RX VIP which passes them up to the OS network stack. The Ethernet MAC/PHY VIP is connected to the SoC design’s interfaces that are both part of the SystemVerilog simulation testbench.
Instead of the OS network stack sending packets via physical media they get sent through the Ethernet MAC/PHY VIP towards the SoC design’s ethernet RX interfaces.
“Leveraging the bandwidth and performance of Ethernet has become increasingly important in a range of data transfer intensive applications and time-to-market is a major concern for product developers. Performing full hardware/software, system-level verification of DPUs, SmartNICs, switches, and routers can be accelerated by weeks to months using virtual network co-simulation. With this solution, any host OS or guest OS (VM) user space program or Linux network utility can communicate with SoC RTL/FW via Avery’s SystemVerilog MAC/PHY virtual NIC VIP,” said Chris Browy, vice president of sales and marketing at Avery.
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