VisualSim memory modelling library boosts algorithm exploration

VisualSim memory modelling library boosts algorithm exploration

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Mirabilis Design has released the VisualSim Memory modelling library, containing all current and prior versions of DDR, LPDDR, HBM, SRAM, JEDEC-compliant memory controller and a generic memory controller.
By eeNews Europe


System designers and architects can use this library to develop new memory sub-systems, explore new standards and algorithms, and optimize the memory access for their target application. The solution has been used to conduct trade-off between different speed/variations of DRAM, performance vs. power, and memory bandwidth efficiency.

VisualSim Memory can be used with VisualSim resource, behaviour and cycle-accurate modelling libraries to construct models, simulate and analyze the complete system or SoC. This library is used to validate proposal, conduct trade-off decisions, timing, throughput, arbitration algorithm, power consumption analysis, and study systems behaviour with different configuration (single vs. dual channels, clock speed variations, addressing schemes, and controller algorithms).

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