VSORA introduces scalable multicore chip for autonomous driving
VSORA’s first full silicon implementation of Tyr is based on the VSORA AD1028 architecture. It can deliver between 258-trillion and 1,032-trillion operations per second while consuming 10W. Tyr allows users to implement autonomous driving functions previously not commercially viable.
Tyr, a family of three different chips called Tyr1, Tyr2 and Tyr3, offers a programmable architecture that couples digital signal processing (DSP) cores with machine learning (ML) accelerators. The Tyr companion chip is algorithm and host processor agnostic and can be integrated into new or existing environments without the need to redesign the system.
Since all processing is done using floating point the processing performance is shown as TFLOPS. VSORA asserts that FP8 provides better performance than INT8 for AI applications while consuming less power. Tyr is initially offered in 3 different configuartions:
Tyr1 – 258 TFLOPS through the use of 64k MACs for AI and 512 ALUs for DSP applications
Tyr2 – 516 TFLOPS through the use of 128k MACs for AI and 1,024 ALUs for DSP applications
Tyr3 – 1,032 TFLOPS through the use of 256k MACs for AI and 2,048 ALUs for DSP applications
“The Tyr family is the first in a series of companion chips from VSORA to provide global vehicle manufacturers early commercial availability of L3 to L5 functionality,” said Khaled Maalej, CEO and founder of VSORA, in a statement.
With a computational power of 1,032 TeraFLOPS, the Tyr3 processes an eight-million cell particle filter using 16-million particles in less than 5ms. A full-high-definition (FHD) image with Yolo-v3 takes less than 1.6ms leading to a throughput of 625 images per second.
The Tyr family is implemented using VSORA’s proprietary architecture to achieve more than 80 percent usage efficiency approximating the theoretical maximum processing power, eliminating the need for expensive multi-chip or hardware accelerator solutions or special cooling solutions.
The VSORA Tyr1, Tyr2 and Tyr3 will sample in 4Q22 and will be available in-vehicle in 2024.
Related links and articles:
Leti, VSORA demo 5G radio on DSP
Automotive SoC combines 500 eTOPS with high-res image and radar processing
Mobileye develops single-chip supercomputer for autonomous driving