VyperCore shows RTL simulation of RISC-V core, plans hardware
VyperCore in the UK has passed a major development milestone in the development of a new chip architecture starting with RISC-V.
Bristol-based VyperCore is developing an architecture to embed functions such as garbage collection to improve the performance of processors and make them more power efficient. It has shown the RTL design for the technology in a RISC-V processor running in simulation for the first time running code and plans a hardware version for June 2024.
“Our technology takes complex and time-consuming memory-related tasks such as Garbage Collection out of software and puts them into the silicon by incorporating them into the processor itself,” said Russell Haggar, CEO and co-founder at VyperCore.
“This eliminates the costly overhead of running these tasks in the background, when you really want the CPU to be focussed on running the user’s application and nothing else. Our technology can be deployed in a way that allows existing software code to run without any changes. During the research phase of our work, we saw applications being accelerated by up to 7x, and we are aiming higher than that with our product development work now.”
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The first processor architecture that VyperCore is supporting is RISC-V. The first processor, called Akurra, is a cleansheet design and takes a standard RISC-V architecture and instruction set, amends the instructions to support the memory allocation technology and implements the substantial alterations to the underlying processor architecture.
Akurra’s RTL is now up and running in simulation. The compiler now supports its extended instruction set, and the runtime passes the garbage collection functionality down to the silicon.
“Our product development involves taking an established processor architecture with a stable software toolchain. We modify the architecture to embed our technology. We update the compiler to support the modified processor, and we change the language’s runtime software to move the memory allocation tasks down to the silicon layer. Clearly, there are a lot of changes here across the whole stack that need to be aligned,” said Haggar.
“This all came together earlier in January when we were able to run standard Python code on the simulated core,” he added.
“This confirms that our technology allows standard, unmodified code to run on VyperCore’s new processor architectures, and it shows that compilers and runtimes can be altered to support our new architecture with minimal changes. This is a major milestone for a company that was funded less than ten months ago, and with a team that’s been up and running for less than six months.
VyperCore was founded in 2022 to productise PhD research into computer architecture design by Ed Nutting at the University of Bristol. Nutting is now CTO and co-founder, and the company now has fifteen staff in design centres in Bristol and Cambridge following a $5m funding round in March 2023. The company also recently joined the Silicon Catalyst accelerator programme and is part of the UK Intel Ignite programme.
“Our next milestone is planned for June, when we will have the next version of the processor running on hardware, not just in simulation,” said Haggar.
“This will let our commercial partners validate that their production code can port with zero effort to our platform, and the accelerated performance will start to be measurable at that point.”
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