Wafer bonding drives 1Tbit flash memory with 218 layers
Kioxia and Western Digital have shown their 3D flash memory technology with 218 layers created with a new wafer bonding technique.
The CMOS directly Bonded to Array (CBA) technology allows each CMOS wafer and cell array wafer to be manufactured separately in its optimized condition and then bonded together for greater bit density and higher NAND I/O speed.
The eighth generation 218-layer 3D flash, sampling now, uses a triple-level-cell (TLC) and quad-level-cell (QLC) with four planes and features innovative lateral shrink technology to increase bit density by over 50 percent in a 1Tbit device. The I/O operates at over 3.2Gb/s, a 60 percent improvement over the previous generation, combined with a 20 percent write performance and read latency improvement.
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“The new 3D flash memory demonstrates the benefits of our strong partnership with KIOXIA and our combined innovation leadership,” said Alper Ilkbahar, Senior Vice President of Technology & Strategy at Western Digital. “By working with one common R&D roadmap and continued investment in R&D, we have been able to productize this fundamental technology ahead of schedule and deliver high-performance, capital-efficient solutions.”
“Through our unique engineering partnership, we have successfully launched the eighth-generation BiCS flash with the industry’s highest bit density,” said Masaki Momodomi, Chief Technology Officer at Kioxia. “I am pleased that Kioxia’s sample shipments for limited customers have started. By applying CBA technology and scaling innovations, we’ve advanced our portfolio of 3D flash memory technologies for use in a range of data-centric applications including smartphones, IoT devices and data centres.
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