Wafer-level SiP yields 5X footprint reduction

Wafer-level SiP yields 5X footprint reduction

Technology News |
By eeNews Europe

Integrating more than 40 different components, the final Fan-Out Wafer-Level Package (FOWLP) solution designed for this customer was produced on large diameter reconstituted wafers, each package measuring only 8x8x1mm, or a fifth of the original PCB design footprint.

"We were challenged by a customer to develop a package with several active and passive components including a large number of SMD parts – so far assembled on a PCB based module – in a single System-in-Package" explained Elisabete Fernandes, the responsible project manager.

"To achieve a small form-factor, we had to attach an active silicon die as a hanging die (WLCSP) at the bottom side of the package inside the Ball Grid Array (BGA). The combination of these technologies enabled highly dense side-by-side (2D) and face-to-face (3D) assembly, ultimately reducing the original space required for this functionality by 5X", she wrote in a company statement.

Nanium says the resulting package was not only smaller, but it also exceeded the previously used PCB based module solution in terms of electrical performance. This was only possible due to the reliance on Wafer-Level Fan-Out (WLFO), the fastest-growing advanced packaging technology in the industry, capable of enabling Wafer-Level System-in-Package (WLSiP) and heterogeneous 3D integrated package solutions (WL3D).

The company has published a new datasheet datasheet "Embedded Wafer-Level System Integration (WLSiP & WL3D)", and will be present its new findings at the upcoming "SEMI European 3D Summit" taking place in Grenoble next week.

Visit Nanium at

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