Wafer-scale CMOS imaging enters X-ray applications

Technology News |
By eeNews Europe

The STFC’s CMOS Sensor Design Group designed a 120×145 mm sensor to be ‘butted’ or ’tiled’ together in a 2 x 2 arrangement, effectively using an entire 200 mm silicon wafer in its production.
The primary target application for the new sensor is X-ray medical imaging and more specifically mammography and digital tomosynthesis, the advanced diagnostic technique used to generate 3D representations of patients or other scanned objects. There is increasing interest in the use of solid-state-based X-ray detection systems in the replacement of conventional diagnostic imaging techniques. One of these technologies is CMOS sensor based imaging, which can bring key advantages in terms of performance such as high resolution, high dynamic range and low noise capabilities.

As no lens is used in CMOS-imaging-based X-ray applications, the size of an image sensor has to match the size of the target area. While in some medical imaging applications such as extra-oral panoramic dental imaging, a sensor measuring 139 x 120 mm is usually adequate, mammography applications require a sensor that is approximately 290×240 mm in size, and even larger for chest radiography. In other applications such as full body scanning for security purposes, an even more extensive sensor area can be necessary.

A three-sided ‘buttable’ sensor design
The new STFC high-resolution and radiation-hard CMOS sensor has been developed to meet these challenges. A unique feature of the device is that it has sensing pixels right up to the edges on three sides of the imager. This allows multiple sensors, manufactured on cost-effective 200 mm silicon wafers, to be ‘butted’ or ’tiled’ together in a 2×2 arrangement to form a significantly larger imaging area and to meet the requirements for mammography applications. Additionally, any 2xN sensor arrangements are possible, thus making the device suitable for applications that demand even larger area coverage, such as chest imaging or security scans.


Traditionally CMOS imagers have the required electronic circuitry implemented on two sides of an imaging array to address the individual sensor pixels. To achieve this three-side ‘buttable’ design, the STFC CMOS Sensor Design Group developed some innovative electronic circuitry IP (Intellectual Property) to implement the necessary pixel readout and row-addressing driver functions on just one edge of each sensor, with extra circuitry embedded in the actual pixel array, while maintaining a high degree of image quality.

The full-custom-design sensor, which offers a focal plane of 139.2×120 mm, has 6.7-million (2800×2400) pixels on a 50-micron pitch, 32 analog outputs and also features low noise, a high dynamic range and a programmable region-of-interest readout. Each pixel is constructed from a basic three-transistor (3T) base with a low-noise partially pinned photodiode, offering ‘charge-binning’ capability to deliver its high signal-to-noise characteristics. This means the sensor can offer a very high frame rate of 40 fps (frames per second) at full resolution and ‘binned’ images can be read at an increasingly faster rate. The high frame rate makes the sensor fit for applications that demand fast acquisition of multiple images such as in digital tomosynthesis, which is receiving increasingly interest in the medical field.

Analog design and manufacturing process
The STFC CMOS Sensor Design Group worked with Tanner EDA and its exclusive representative in Europe, EDA Solutions, to use the Tanner tools to develop the innovative pixel-addressing IP, which was almost entirely analog circuitry with only a small amount of on-chip digital logic. Specifically, the STFC design group used Tanner Tools Pro, in conjunction with Tanner’s HiPer Verify tool. Tanner Tools Pro is a comprehensive software suite for the design, layout and verification of analog, mixed-signal, RF and MEMS ICs. The tool suite comprises fully integrated front-end and back-end tools including schematic capture, circuit simulation, waveform probing, physical layout and verification. Tanner’s HiPer Verify is an affordable solution for analog and mixed-signal IC design rule checking (DRC) and hierarchical netlist extraction.

The STFC design group also worked closely with TowerJazz for the manufacture of the sensor, which is implemented in a 180/350-nanometer dual-gate CMOS Image Sensor (CIS) process technology on 200 mm wafers. TowerJazz’s CIS technology process enables the customization of pixels, according to project needs for many digital imaging applications, offering excellent dark current, low noise and dynamic range performance characteristics.

Visit the Science and Technology Facilities Council (STFC) at


Linked Articles
eeNews Europe