Webinar; Error-correction IP cuts spurious products in high-speed ADCs

Webinar; Error-correction IP cuts spurious products in high-speed ADCs

Technology News |
By eeNews Europe

In this webinar, Teledyne SP Devices’ ADX time-interleaving ADC IP will be explained, detailing the use of a digital block for the post processing of the output from interleaved ADCs and how it can be used with any ADC. The ADX technology features both the estimation of mismatch error and the reconstruction of the signal with all mismatch errors suppressed.


Time interleaving of analogue to digital converters (ADCs) is a way to increase the overall system sample rate by using several ADCs in parallel. The challenge is to handle the mismatch between the individual ADCs, especially at higher frequencies, and error-correction IP helps correct the manufacturing variations of the characteristics of the individual ADC, in order to obtain the optimal resolution.


A custom version of ADX has been implemented into the EV12AS350 from Teledyne e2v, a 12-bit 5.4 GSps ADC with input bandwidth over 4.8 GHz, and demonstrates the proprietary technology of ADX continuously providing a background estimate of the gain, offset and time skew errors of the ADC, without the need for any special calibration signal or post production trimming. The patented reconstructor block recreates the signal with minimal latency, in this scenario enabling over 20db of improvements to time-interleaved spurious effects.


The webinar will be broadcast at 7:00pm (19:00) BST/ 20:00 CET, on 29th September. Registration is required, on this page, where there is also information on presenters Kurt Rentel, BDM, Teledyne e2v; and Per Löwenborg, Vice President and General Manager, Teledyne Signal Processing Devices.

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