Weebit moves SiOx ReRAM on to 40nm

Weebit moves SiOx ReRAM on to 40nm

Technology News |
By Peter Clarke

The 40nm scaling shows that the technology can be scaled down to advanced geometries, and makes the technology relevant to multiple applications such as mobile phones, laptops and the Internet of Things, Weebit said. The company added that it had achieved this in two years while other ReRAM companies had taken 10 years

 This has been achieved ahead of schedule and quickly after successful data retention and cycling endurance testing of a 4kbit array of 300nm memory cells earlier this month (see Weebit scales SiO2 ReRAM to 4kbit).

Lifetime extrapolation showed the technology’s ability to retain data for 10 years at above room temperature. In addition, the chips maintained their data after 30 mins at 260 degrees C. This exceeds the solder bath requirement of 15 minutes at such temperatures allowing preprogrammed NVMs to be added to PCBs prior to wave soldering.

The 40nm memory cells on various wafers verified the ability of Weebit Nano SiOx ReRAM cells to maintain memory behaviour in accordance with previous experiments performed on 300nm cells.

“Demonstrating such an advanced geometry paves the way for us to further develop our technology by scaling up array capacities for use in different applications and integrating into deeply scaled down CMOS technologies that are used in all processors, RAM and digital logic circuits on most small devices,” said Coby Hanoch, CEO of Weebit Nano in a statement.

Next: What the chairman said

David Perlmutter, Weebit chairman, said: “Our development strategy, which focuses on unique IP that capitalises on known manufacturing processes, is paying off with fast and flawless execution. What took other companies up to 10 years to achieve, took Weebit Nano less than two years, thanks to our unique approach of focusing on standard silicon oxide which does not require any special equipment or processes.”

Weebit said it plans to start scaling up capacity into kilobit and megabit array structures in 40nm manufacturing process during the first half of 2018 while working on its technology roadmap beyond 40nm and on industry collaborations.

Related links and articles:

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Two test vehicles planned for SiO2 ReRAM

Weebit scales SiO2 ReRAM to 4kbit

Startup to exploit piezomagnetism for memory

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