Weebit qualifies ReRAM for production on 130nm process
Weebit Nano Ltd. (Hod Hasharon, Israel) has qualified its Resistive Random-Access Memory (ReRAM) technology to JEDEC guidelines on a 130nm bulk-CMOS manufacturing process provided by R&D partner CEA-Leti.
The qualification on Weebit demo chips incorporating its ReRAM, was performed based on well-known JEDEC industry standards for non-volatile memories (NVMs). It confirmed the suitability of Weebit’s embedded technology for volume production as embedded IP. This is the first full qualification of Weebit ReRAM technology, a key step that must be completed for every semiconductor product on each target process.
Weebit’s ReRAM, one of a number of emerging non-volatile memory technologies, is based on metal ion and oxygen vacancy migration to make and break a filamentary conduction path in a memory cell. The company was launched in 2014 on the basis of switching resistance in thin films made of nanoporous silicon oxide. For more advanced manufacturing processes it is believed that Weebit has moved on to using hafnium-based oxides that are used as insulator materials close to the silicon surface (see Weebit moves ReRAM on to ‘secret-sauce’ materials)
The demo chip includes a 128kbit ReRAM memory integrated with a RISC-V microcontroller, system interfaces and peripherals. There are similarities to a similar test chip taped out by SkyWater Technology in its 130nm CMOS process (see Weebit tapes out ReRAM demo chip with SkyWater foundry).
The qualification showed the ReRAM has better than 10K cycling endurance and ten-year data retention before and after endurance testing, as well as industrial-grade 85 degree C high-temperature stability. In this it performs as well or better than embedded flash while bring the advantages of simpler integration and low power consumption. The tests also demonstrated data retention under three surface mount technology (SMT) reflow cycles (up to 260 degrees C).
Weebit is now working to extend the qualification to higher temperatures and endurance levels.
Microcontroller calling card
Eran Briman, vice president of marketing and business development, said 128kbit and 256kbit non-volatile memory arrays are a sweet spot for some microcontroller applications. “We are moving forward with a 22nm FDSOI tape-out before the end of the year. At that place you need a much larger memory array – 8Mbit – and embedded flash is not an option.”
Briman confirmed that Weebit is building the memory array directly on top of the silicon and using a select transistor as the matrix-isolation device – rather than an ovonic threshold switch.
“Leti’s state-of-the-art fab makes these qualification results significant and relevant for other foundries and potential customers and could be used by customers as a baseline for their qualification process. We are now engaged at various stages with multiple Tier-1 foundries and semiconductor companies, and having achieved this milestone, our activities with potential customers are accelerating,” said Coby Hanoch, CEO of Weebit Nano, in a statement.
The Weebit ReRAM demo chip comprises a full sub-system for embedded applications, including the Weebit ReRAM module, a RISC-V microcontroller (MCU), system interfaces, memories and peripherals. The ReRAM module includes a 128Kb ReRAM array, control logic, decoders, IOs (Input/Output communication elements) and error correcting code (ECC). It is designed with unique patent-pending analog and digital smart circuitry running smart algorithms that significantly enhance the memory array’s technical parameters.
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