Weebit scales SiO2 ReRAM to 4kbit

Technology News |
By Peter Clarke

As a result the high-speed non-volatile storage previously achieved on a singl cell has now been replicated on a 4kbit memory array cell structure. The company’s next goal is a 40nm ReRAM silicon oxide working cell by the end of 2017, which the company said it is on track to meet.

An experimental wafer demonstrated a 100 percent pass rate for “forming” and “set and reset” distributions after several program and erase cycles. Preliminary speed tests have demonstrated write” speeds 100 to 1000 times faster than traditional 3D flash technology while using significantly lower energy, the company said.

“After extensive characterisation of 300nm cells, we have now achieved a significant step forward by successfully scaling up to the 4kbit array structure,” said Coby Hanoch, CEO of Weebit Nano. “Not only have we verified very fast writing speed and

that our resistivity distribution on the wafer was very narrow, we were also able to demonstrate that the cells can be grouped into a standard 4kbit array without interfering with each other.”

The 4kbit array characterisation results were achieved in Leti’s facilities in Grenoble, France.

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Two test vehicles planned for SiO2 ReRAM

Leti to develop SiOx memory with Weebit Nano


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