Processing-in-memory is a technique that uses memory arrays as analogues of neurons in synaptically-connected neural networks. This allows the memory element to function as both a logical and storage device and makes memory values available where they are needed.
This differs from traditional von Neumann computing architecture that separates the central processing unit from memory. These read and write transactions require significant amounts of time and energy, increasing power consumption and introducing latency, which also contributes to power consumption.
Perform computation inside the ReRAM arrays is much faster and uses up to 1,000-times less power by avoiding the need to export and import data between the memory chip and CPU, said Weebit.
A team at Technion, led by Professor Shahar Kvatinsky, a pioneer in the field of circuits and architectures with emerging memory technologies and design of energy efficient architectures, will perform characterisation and implementation of logic operations using Weebit’s SiOx ReRAM test chips, demonstrating basic logic operations on a ReRAM array using Technion’s so-called MAGIC technique (Memristor Aided Logic) to implement PIM.
“We believe that ReRAM, in addition to being the next-generation memory element, will also be a part of the computing revolution enabling novel architectures mixing logic and memory to allow significantly power efficient real processing-In memory computing,” said Coby Hanoch, CEO of Weebit Nano, in a statement.
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