What about DC Power Integrity? – Part 2
Part 1 of this article outlined the basic principles of ensuring power integrity (PI) on a PCB; at symptoms that reveal your board may have a PI problem; and at extracting some key figures from active device data sheets; Part 1 is here.
Monitoring tools for embedded systems
One useful function offered by modern embedded tools is the ability to monitor power consumption in concert with debugging code. Various means of measuring power are provided.
For example, the STM32429IG-EVAL board from ST Micro, which uses a variant of the ARM processor mentioned in Part 1 of this article, is designed with a jumper in place for the VDD rail to the CPU. The intent is that while you are developing and debugging source code you can be measuring the current being supplied to the CPU:
1. Set a breakpoint at the beginning and end of the code routine of interest.
2. Enable the oscilloscope trigger on the current measurement probe on JP2.
3. Step into the routine, capturing the current waveform on the ‘scope.
4. Repeat for all routines of interest, taking note of the current requirements.
This way, you can get a clear picture of how the source code is affecting power consumption, and even decide how to modify code to optimise or limit power usage.
Similar tools are available for monitoring FPGA development flows. Figure 4 shows the power monitoring capability of the NanoBoard FPGA development board. In this example I am running the C-to-Hardware reference design that spins a graphical cube in 3D. I can switch between processing the matrices for transformation in software and FPGA hardware, and compare the power consumption based on how the job is done. Similar tools can be found with FPGA vendor development boards as well.
Figure 4. Monitoring power consumption during FPGA/Software debug of a System on Chip design.
Working with DSO or PC-based instruments along with the embedded debug tools even give you an edge in developing lower power code. Figure 5 shows this in action with “PowerScale” (from Hitex, which works alongside Altium’s TASKING C/C++ development tools).
Figure 5. Using high-speed current probes with the development board.
In this case it’s easy to measure peak and average currents required by your source code over the software execution lifecycle. But what can you do to ensure that your custom PCB design can cope?
So what’s it to do with DC Power Integrity?
Modern designs are complex, and with limited space to design the power network on the PCB, and with ever shrinking device packages, it’s getting hard to use the old brute force “plenty of copper” approach to providing power to these devices. Knowing about these techniques will be key in using a multi-pronged approach to solving power integrity bottlenecks at the PCB design level also.
A PCB fuse trick?
Before I dive in, however, let me share a little story. When I was a wet-behind-the-ears college student, I had a part-time job doing PCB design and assembly at a “ma and pa” electronics company in my hometown. They were really cool people, and I learned a great deal about PCB design and hand prototyping, design for assembly, and testing from the proprietor. I was impressionable in those days, and one thing he impressed me with at the time was how he used to design fuses into his PCBs with thin trace segments, and a component land pattern for a real fuse should the PCB trace need “replacing”. The fuse was apparently rated at 2A, and was a 10 mil (0.010 in./0.25 mm) width in standard 1oz. copper. I wondered if he had some magic formula or if he had empirically chosen the width. He wouldn’t tell me…
There are several factors at work in the PCB which can undermine longevity or performance, not the least of which is temperature change. We normally do consider temperature rise, because what we really want to know is how to prevent failure or damage due to overheating. But more generically, large temperature swings can also limit the useful life of the product due to other thermo-mechanical stresses.
next; polygon ‘necks’…
Polygon neck-down
Every experienced board designer knows the headache of design trade-offs. For example, when the allowed layer count, component placement (i.e. 3D mechanical requirements), and difficult routing all conspire to bring unavoidable neck-downs in power distribution polygons, like the one shown in Figure 6.
Figure 6: The 1V8 power supply to the camera module on the STM3240G-EVAL board.
Intuitively this looks like a bottleneck we want to avoid. But the question is, will it be a problem in the actual use of our device? Figure 6 shows a 1V8 power supply net polygon which takes the 1.8V supply rail from the linear regulator’s output to a small camera module (the kind of camera your kids are taking ‘selfies’ on). Additionally there’s an extension camera header connector for the board to allow more substantial external cameras to be connected to the board. The main camera module only draws 50 mA or less, so it’s unlikely to cause an issue, but plugging something external into the extension header could cause an issue.
Heating copper
To work out the basics of the problem, remember that the etching process leaves the copper traces (in this case the polygon’s narrow point) wider at the base – with a trapezoidal cross-section like the one shown in Figure 7. Heating and fusing of the copper begins as a typical Joule Heating problem.
Figure 7: Trapezoidal shape of the PCB copper conductor at the neck-down or trace.
Quick high school physics review: the amount of energy transferred due to work done (i.e. power dissipation by time) is directly proportional to a change in temperature in the material in question. In our case the power dissipated from a tiny bit of PCB copper like that shown in Figure 2 is easily calculated by using the resistivity of copper.
Where Q is the energy transferred in Joules; m, the mass of the copper; c the specific heat of copper (about 0.387 KJ/KgK) and ΔT the change in temperature. Q relates the change in temperature to the power dissipation for a given time. And since P = I2R, Q = I2Rt The resistance of the copper is based on the area, length and resistivity:
Where ρ for copper is 1.68 x 10-8 ohm-meters at 23C, L is length and A is cross-sectional area. So in a basic sense we can figure out trace temperature rise in the trace based on the DC current and its cross-sectional area:
However, this is neglecting the conduction of heat away from the trace into the board and convection of surrounding air, and it is also neglecting the fact that copper resistivity is a function of temperature – the resistance of the trace or neck-down rises as it gets hotter. Combine this with the arbitrary nature of board design (differing materials and layer stacks), and you come to realise the only completely accurate way of calculating the temperature rise in the conductor of interest is to use a coupled electrical and thermal conduction model, in a finite-element analysis tool.
next; fusing time and current
Fusing time and current
But there has been good research done over the last decade to produce a few empirical models that can predict temperature rise accurately enough for standard PCB applications. One of our main concerns is; can the trace or neck-down region cope with the current required in the design without fusing?
The PCB design community has followed the lead of people such as Douglas Brooks [1] on this one, who cites Onderdonk’s equation (a curve-fitted model of circular conductor fusing current):
And a simplified version:
These were formulated a long time ago, using copper wire with circular cross-sectional area A in square mils, time t in seconds to fusing, and the melting point of copper, Tm, in °C. Ta is the ambient temperature. The simplified version has been used by PCB designers and in various calculators and toolkits for a long, long time. It’s nice and convenient because it relates fusing time directly to current and area – in other words current density. However it results in grossly pessimistic fusing current estimates for PCB traces – namely because of the heatsinking effect of the surrounding board materials and copper planes. Some like to use it still because this pessimism results in boards with a large margin of safety. It’s pretty easy to make a tool to apply these – as shown in the spreadsheet shown as a screenshot, in Figure 8.
Figure 8. Calculating fusing current, current density, and power dissipation of a small PCB track segment.
But this can backfire! Looking back at those “PCB fuses” I realise that this was how my old boss had calculated the “about 2A” with a 10-mil wide track. I also realise how dangerous this idea is and why you should never use PCB traces as fuses intentionally. Because the fusing current is invariably much higher than that predicted by Onderdonk’s (and also Brook’s) equations. This means a fault can occur well above the current at which you expect the fuse to protect the system, and it may not blow at all.
Moreover, the melting point of copper is 1083°C, but the glass-transition (Tg) temperature of FR-4 epoxy is usually about 140°C. At this temperature, the epoxy starts to go soft and gooey again. I am much more interested in making sure that the PCB doesn’t fail because of this. If the board has hot regions that approach Tg (bear in mind the Tamb of the product), all sorts of reliability problems will arise: delamination, blistering, dielectric breakdown, lost impedance control, and more. Not to mention wasted energy in a world ever more concerned about reduction, recycling, reusing.
next; real-world measurements…
Fortunately a little more recently, Jouppi et. al. [Ref. 2] bothered to take the time and actually measure temperature rise in copper traces in a controlled environment, with board samples that tested both internal and surface layer traces. What they found was a series of curve-fitted current functions of measured temperature rise I(∆T). Figure 9 shows a snippet of curves – generated by Jouppi’s fitted formulas for several ½-oz. copper trace widths in internal FR-4 layers:
Figure 9: Temperature rise curves from Jouppi’s fitted equations.
The widths and thicknesses of these traces (internal to the board) were measured using microsections. These are particularly useful, because they directly relate current and temperature rise. I wanted to see if Jouppi’s measurements indicated a set current density for a given temperature rise, so a quick re-calculation of the steady-state temperature rises versus current density resulted in figure 5 below:
Figure 10: The same temperature rise plotted versus current density.
Notice that I kept the line colours the same for each of the trace widths. It may appear counter-intuitive at first, that the wider traces exhibit greater temperature rise with lower current densities. I’m no expert on thermodynamics (perhaps someone who is could help explain this to me) but I believe this is due to the larger thermal mass of the wider traces, coupled with the reduced surface area to volume ratio. For instance, the increased relative surface area of the 5mil (0.12 mm) trace allows faster energy transfer into the surrounding board materials.
Going back to the question of the board I’m working with, I can analyse the current density for a load on the connection of about 250 mA, using a 2D solver. The probe result of the neck-down in question shows a simulated current density of about 14E+06 A/m2, shown in Figure 11. The neck-down is 5mils wide at the narrowest point.
Figure 11: Using Altium PI-DC, probing the neck-down for simulated current density.
Comparing this with the graphs above for ½ oz. copper, we would have a temperature rise of only a few degrees. So although it’s mildly wasteful of energy, the board isn’t going to blow up.
Jouppi’s thorough investigation was a landmark for PCB designers. These curves, generated by tightly controlled experiment environments, lead to the development of the most accurate tool yet for determining current carrying capacity in PCB traces and plane neck-downs. The IPC-2152 standard that resulted is a document that every PCB designer should have at their right hand when designing the PCB’s power distribution network. Finding the current density in power net polygons will go a long way to ensuring you’re well within safe limits also. But current density is not only a concern for thermal reasons. In sufficiently small metal interconnects, high current densities can result in electromigration, which can lead to failure. But more on that some other time…
References:
[1] Douglas Brooks, “Temperature Rise in PCB Traces”, Proceedings of the PCB Design Conference, West, March 1998.
[2] Michael R. Jouppi et. al., “Current-Carrying Capacity of PWB Internal Conductors in Space Environments”, 2000 Inter Society Conference on Thermal Phenomena, IEEE, 2000.
About the author
Ben Jordan is senior manager of content marketing strategy at Altium.
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