What does a spin qubit look like?
Belgian research lab imec has detailed the spin qubit technology it is building on 300mm CMOS wafers, marking a significant scaling of quantum processing technology.
The two qubit device has a stability of 99% and shows a route to scaling large quantum processing unit (QPU) chips
The key metrics including single- and two qubit control fidelities exceed 99 % and state preparation and measurement fidelity exceeds 99.9 %, as shown by gate set tomography (GST).
The coherence and lifetimes, vital for quantum computer operation, are up to T ∗ 2 = 30.4 µs, T Hahn 2 = 803 µs, and T1 = 6.3 s. Crucially, the dominant operational errors originate from residual nuclear spin carrying isotopes which are solvable with further isotopic purification, rather than charge noise arising from the dielectric environment.
“Our results answer the longstanding question whether the favourable properties including high-fidelity operation and long coherence times can be preserved when transitioning from a tailored academic to an industrial semiconductor fabrication technology,” say the researchers.
The fabrication starts with epitaxial growth of an isotopically enriched layer of silicon with a residual concentration of 400 ppm 29Si silicon. A high-quality thermally grown oxide forms the Si/SiO2 interface at which the charge of the electron spin qubit is accumulated.
Next, a triple-layer overlapping polysilicon gate stack is formed using EBL and etch processes, with each gate separated by a thin interstitial high-temperature oxide deposition.
Finally, an aluminium stripline to manipulate single spin states using electron spin resonance (ESR) is patterned in proximity to the device as an intermediate control solution at the few-qubit level.
The design consists of a double quantum dot and a nearby single-electron transistor (SET) for spin readout, operating at 10 mK.