What is the best PLL configuration for your app–and how do you find it?
The goal of any frequency synthesizer is to generate a desired output frequency based on a given input reference frequency. However, this relationship between available input frequency and required output frequency is not always obvious. The question always looms: Is there another, better configuration for my PLL that will deliver better noise performance and lower power? Sometimes the question is a critical as whether the current hardware is even able to meet new requirements (does a solution exist?) This article introduces a method for finding all possible PLL configurations (using integer divide PLLs) that can meet a given set of input / output frequency requirements. A metric is then applied to this complete list of configurations to determine the best configuration for your specific application.
Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL. Specifically, we will need to be able to find all of the possible configurations that our PLL can use for a given reference oscillator and desired output frequency. Once we are able to confidently generate the list of all possible configurations that satisfy our needs, we can then choose which one is best. Actually, the bulk of the work in determining an optimal PLL configuration is wrapped up in determining the list of all possible configurations that meet our needs. As such, this article will first focus on determining all possible configurations, then wrap up with selecting the best option.
An Overview of Integer Divide PLL Frequency Synthesis
At the most fundamental level the goal of any frequency synthesizer is to, based on a given reference frequency, generate a desired output frequency. That is, solve:
where K is the frequency scaling constant, sometimes referred to as the normalized frequency. Any frequency synthesizer circuit is simply a mechanism for approximating K. A survey of methods for generating K is beyond the scope of this paper. Here we will focus exclusively on integer divide PLL frequency synthesizers. A PLL frequency synthesizer approximates K by inserting divide blocks between the reference oscillator and the output clock. Then, using a feedback loop with a phase detector to maintain phase coherence between the two dividers, the desired output frequency is generated. The block diagram for this is shown in Figure 1. This is the general form of a charge pump integer divide phase locked loop.
Three divide blocks are used to approximate the value of K: the reference divider (Q), the feedback divider (P), and the output divider (N). It can be readily shown that K is defined for this type of frequency synthesizer as:
Combining equations 1 and 2, the relationship between input and output frequency is:
Common variants on the general form shown in Figure 1 are to set N equal to one, Q equal to one, or both. These simplifications are based on system design needs. Analysis of all three of these simplifications is a subset of the general case shown in Figure 1. If both Q and N are set equal to one, then the maximum resolution of the output frequency is limited to the reference frequency, making it possible to synthesize only integer multiples of the reference. In this case, determining the value of P is reduced to a simple matter of arithmetic. If just Q or N is set equal to one, then only a single configuration exists (with respect to a minimum Q/P or N/P ratio) for synthesizing the desired output. Determining this ratio is then a matter of fraction reduction.
The use of all three-divide blocks introduces an added layer of generality to the hardware that enables the direct reuse of the PLL through programming for many different frequency synthesis applications. However, this generality also results in a significantly more complex problem in determining the values of P, Q, and N to use. Specifically, it results in multiple configurations existing for a single reference and output frequency, all of which can have drastically different performance characteristics (power, startup time, jitter, phase noise, etc).
An additional configuration that is used in programmable SoCs is to have multiple output dividers. This allows for the generation of multiple outputs at different frequencies (but are still integer multiples of the VCO frequency). Figure 2 illustrates this configuration.
Finding All Possible Configurations for a Programmable PLL
So then, given a set of system requirements, how do we select divide values for P, Q, and N? First let’s look at (3) in a slightly different form, putting all the known values on the right hand side, and unknowns on the left:
The difficulty in solving (4), for any arbitrary reference and output frequency, is that there are three degrees of freedom (limited only by the range of divide values P, Q, and N can take on). The most common technique for solving (4) is a search algorithm. Such algorithms work by searching the solution space, looking for sets of P, Q, and N values that will result in the desired value. They are, in essence, triple-nested loops that search all possible P, Q, and N values. Such search algorithms are used in most PLL configuration software. Conceptual pseudo code for how this type of algorithm is implemented is shown in figure 3. Note that many practical system constraints have to be added to this code for it to reliably produce only useful configurations.
An Illustrative Example
For this example, we will synthesize a 50MHz output from a 14.3181818 MHz reference (a common video application frequency). Assume the VCO has a frequency range of 100MHz to 400MHz. Using a search algorithm similar to that shown in Figure 3, we generate the results shown in table 1. This is the list of all possible configurations that will fit our needs. Now we need to select the best option.
Choosing an Optimal Configuration
Now that we have found all configurations that meet our frequency needs, we can turn our attention to selecting the optimal configuration. The best configuration is completely application-dependent. For a remote monitoring station, for example, we may need to wake the part up quickly but not need it to be very accurate. For a communication protocol, we may not care about startup time or power consumption but need an extremely low jitter clock source. Or we may need both: during data collection we may just need fast wakeup, but during data transmission we need high accuracy. With a programmable PLL and a programmable SoC, you can have both. You just need to know which configurations to use.
Here we will discuss several common PLL parameters that are optimized in various applications. Table 2 summarizes these parameters, the corresponding key loop parameters, and how to optimize them. Note that not all programmable PLLs will give you access to all parameters listed.
Power is dominated by the VCO frequency, charge pump current, and divide block settings. Most VCO architectures require larger tail currents to achieve higher frequencies. This means that as frequency increases, so does power consumption. Charge pump current is discharged once for each PFD period. When larger charge pump currents are required (for loop stability or fast startup/settling time), more power is consumed per PFD period. Clock dividers dissipate power at each clock edge. Larger clock divide values require more divide cells to transition, consuming more power.
Startup Time/Settling Time
The startup and settling time for a charge pump PLL is dominated by the loop natural frequency. This parameter can be thought of as the frequency slew rate of the PLL. It quantifies how fast the PLL can change the output frequency. It is proportional to the VCO gain and charge pump current, and inversely proportional to the feedback divide value and loop filter capacitance. To minimize startup time, we need to maximize VCO gain and charge pump current, and minimize the feedback divide setting and loop filter capacitance.
Similar to startup time/settling time, the PFD frequency and VCO gain play a key role in Jitter. Higher PFD frequencies mean that the PLL loop filter voltage is refreshed at a higher rate. This prevents the loop filter voltage from drifting. By using a large loop filter capacitance, the amount of voltage drift per PFD period is minimized. Because the VCO gain dictates how far the output frequency drifts per unit voltage drift on the loop filter, lower VCO gain makes the PLL less sensitive to loop filter voltage drift.
Optimizing phase noise is highly application-dependent, but a few observations can be made. In general, phase noise contributed by the reference oscillator can be suppressed by setting the PLL to a lower closed loop bandwidth. Phase noise contributed by the VCO can be suppressed by setting the PLL to a higher closed loop bandwidth.
One parameter that can be controlled to reduce phase noise is the output divider (N). Phase noise divides proportional to the output divide setting. If the output divider is a low noise divider, then running the VCO at a higher frequency and dividing the output frequency down will result in a phase noise improvement.
Optimizing the Illustrative Example
Finally, let’s apply this general discussion on optimization to the list of PLL configurations that we found in the above example.
If low power consumption is the primary design concern, we want to minimize VCO frequency and divide values. Selecting the N=3, Q=21, P=220 configuration would be the best choice. This operates the VCO at one of the lower frequencies, lower P and Q values, and has a reasonable PFD frequency.
Startup / Settling Time
If startup / settling time is the primary concern, then from table 1 it is clear that the N=7, Q=9, P=220 configuration is the most desirable. It has an fPFD of more than two times any other configuration, resulting in a higher refresh rate on the loop filter voltage.
If low jitter is the primary concern, then the N=7, Q=9, P=220 configuration is again the most desirable. It has an fPFD of more than two times any other configuration, resulting in a higher refresh rate on the loop filter voltage, and the lowest jitter of all the possible configurations. The difference from optimizing Startup/Settling Time is that a large loop filter cap and lower Kvco should be selected for low jitter.
Optimizing phase noise is highly application-dependent and depends on specific reference oscillator and VCO noise performance. The one design choice we can make based on our configuration list is to choose a high VCO frequency that is divided down. The N=7, Q=9, P=220 configuration is probably the best because its PFD frequency is so much higher than the N=8, Q=63, P=1760 configuration. If the loop has high jitter, then the phase noise floor will rise significantly, swamping out any improvement the output divider is giving us.
About the Author
Erik Mentze is a Senior Systems Engineer with Cypress Semiconductor developing system validation tests and test methodologies for their programmable system-on-chip product line.╩ He holds a Bachelors of Science degree in both Mathematics and Electrical Engineering from the University of Idaho, as well as a Masters of Science degree in Electrical Engineering from the University of Idaho. Previously he has been a part of Cypress’ programmable clock and wireless transceiver design groups, developing re-programmable, high spectral purity, frequency synthesis PLLs.
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