A Reusable Verification Environment for a RISC-V Vector Accelerator
This paper from DVcon Europe presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors.
In order to be used across diverse projects, this infrastructure intends to be independent of the interface used for connecting the accelerator to the scalar processor core. The verification infrastructure consists of a Universal Verification Environment (UVM) which is capable of validating the design performing co-simulation of the vector instructions as well as a set of tests and an automated test generation, simulation and error reporting infrastructure.
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