Buffer Architecture for generating delay
By
Freescale Semiconductor
The conventional buffer cell design is not able to provide the desired delay needed for hold fixing and if a lower strength buffer needs to be used for more delay then that buffer suffers from noise.
All these shortcomings motivated us to develop a new buffer cell that is capable of meeting hold timing without any impact in area, and having a high delay with the same noise immunity, i.e., a cell with more delay and with the same drive strength so that it’s noise immunity also remains same.
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