Characterizing Standard Cell -Part 1

By Freescale Semiconductor India Pvt. Ltd.
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Increasing demand for enhancing the quality and timing complexities of the ASIC designs calls for keen characterization of standard cells. To cater to the requirement of timing calculation, EDA tool must rely on the delay models of individual cells. Unfortunately, no standard delay calculation model has been adopted till now and most of the key vendors have their own methodologies for delay modeling depending upon the application and technological requirements. While most ASIC designers are familiar to the word library, very few are well versed to the methodology followed while characterizing it. Familiar to the fact that PVT corner can hamper the delay of the cell set, the paper deals with the methodology to find the delay and characterizing instead of going in details of PVT corner based library set. This paper discusses the models and methodology that are used commonly for combinational delay estimation in standard logic cells. Additionally, it focuses on the influence of transistor ordering and restructuring that can affect the cell delays. Read More

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