Choosing and Using GaN Technology for High-Efficiency Power Conversion
Wide bandgap (WBG) power switches have emerged to tackle these challenges. Replacing conventional silicon power semiconductors with WBG devices in could increase typical DC/DC converter efficiency from about 85% to nearer 95% or boost typical DC/AC inverter efficiency from 96% to 99%.
Among WBG devices in the market today, gallium nitride (GaN) high electron mobility transistors (HEMT) offer significant advantages over existing silicon-based alternatives such as superjunction transistors, up to voltage ratings of about 600V. Advantages include significantly lower input and output capacitances (Ciss and Coss), which results in lower switching losses. Also, the Miller capacitance of a GaN transistor is much lower than for a MOSFET of comparable RDS(ON). Hence the GaN device can be turned on and off much faster, which, in turn, permits the use of smaller transformers and passive components. Also, lower on-resistance per die area leads to reduced conduction losses and frees designers to achieve a favorable trade-off between energy losses, device size, and the cost and size of thermal management such as heatsinks.
GaN in the Market
Until recently, GaN technology has been prohibitively expensive compared to more established silicon-based alternatives. The development of the superjunction transistor, unlocking further improvements in the figure of merit for silicon technology, has been one factor that has held back widespread adoption of GaN devices. Now, however, as further development and economies of scale make GaN more economically viable, and the pressing demand to improve power-conversion performance and efficiency further still, GaN devices are ready to gain more and more design wins.
Fundamentally, GaN power transistors are either depletion-mode devices, which are normally-on and require a negative gate voltage relative to the drain and source electrodes to turn off, or enhancement-mode, or e-mode) devices. These usually are off and are turned on by a positive gate voltage.
Depletion-mode devices can deliver higher performance and robustness, although careful management of system start-up to avoid potentially dangerous short circuits. In a half-bridge topology containing depletion-mode GaN FETs as both the upper and lower switches, for example, the gate control circuits must be started first to supply negative bias and keep the transistors off, to prevent powering-up the DC bus into a short circuit. An alternative is to use a depletion-mode GaN transistor in cascode configuration with a low-voltage silicon MOSFET. As figure 1 shows, the GaN transistor source is connected to the silicon MOSFET drain, and the silicon MOSFET source is connected to the GaN transistor gate. When no bias is applied to the silicon MOSFET gate, its drain-source voltage (Vds) negatively biases the GaN transistor gate, to keep the device turned off. Co-packaged cascode GaN power transistors such as the ON Semiconductor NTP8G202NG are already in the market.
Figure 1: Cascode configuration delivers GaN performance advantages with normally-off convenience.
An enhancement-mode GaN HEMT, being normally off, eliminates short-circuit concerns on start-up. A 650V GaN device further simplifies design-in by operating from a low gate voltage of only 0-6V and tolerating transient voltages at the gate as large as-20 to +10V. With six contacts and a package designed for bottom-side-cooling, as well as low on-resistance 25mΩ, it can handle drain-source current of up to 10A, while switching frequency can be as high as 10MHz.
Switching Circuit Design
Like any other power devices, GaN transistors need a properly matched and configured gate driver to ensure the device is turned fully on and off, quickly, with no unintended issues. To achieve this, the driver must be able to quickly charge the transistor’s gate capacitance to turn the device on, without inducing ringing or overshoot. When turning off, it must quickly discharge the gate, again without ringing or overshoot. Consistent performance and proper skew-time control are essential, to avoid “shoot-through” short-circuits in bridge configurations.
There are three key factors to consider when driving GaN devices. These are the maximum allowable gate voltage, the gate threshold voltage, and the body diode voltage drop. Because the gate-source voltage for such an enhancement-mode GaN device is 6V or roughly half that of a MOSFET, it is easier to generate the turn-on/turn-off voltages and currents required. The gate voltage also has a lower negative temperature coefficient, which simplifies driver compensation. The forward-voltage drop of the transistor’s intrinsic body diode is about 1 volt higher than comparable silicon MOSFETs.
Overall GaN turn-on times are about four times faster than MOSFETs with the same RDS(ON), while turn-off time is about twice as fast. Although this brings system-level advantages, extra care is needed when considering the dynamic issues of the driver and associated circuitry. dV/dt slew rates can be faster than 100 V/nsec, which can affect efficiency adversely by creating a shoot-through condition between paired devices in a bridge during the switching transition.
To prevent this, the gate-drive pull-up resistance can be adjusted to achieve the fastest desirable transition time without inducing other unwanted loss mechanisms. In addition, this helps avoid overshoot and ringing and so can prevent false turn-on/turn-off glitches and minimize EMI generation. In practice, it may also be necessary to add ferrite beads in series with the gate to reduce high-frequency LC-ringing and overshoot, and possibly adding an RC “snubber” across the gate-source path.
Figure 2 (below) summarizes the GaN transistor’s turn-on behavior graphically and highlights the issues that need to be considered to ensure reliable operation. Similarly, figure 3 illustrates the turn-off case.
Figure 2: Factors to consider when arranging GaN-transistor turn-on. (Source: GaN Systems).
Figure 3: GaN-transistor turn-off situation (Source: GaN Systems).
For GaN devices where the threshold voltage is low, the pull-up resistance can be optimized individually for turn-on and turn-off conditions by merely splitting the gate pull-up and pull-down connections in the driver to allow a discrete resistor to be inserted (Figure 4).
Figure 4: Independently optimizing turn-on and turn-off resistances helps to minimize undesirable effects (Source: GaN Systems).
Optimizing the gate turn-on/off resistor ratio is necessary to maximize drive performance as well as stability. The turn-on gate resistor is typically between 10 and 20Ω. If it is too large, the turn-on dV/dt slew rate is reduced, leading to slower switching and increased losses. Conversely, if the slew rate is too low, switching losses can result from Miller-effect turn-on as well as potential gate oscillation. If the turn-on gate resistor is 10-20Ω, a turn-off resistance of about 1-2Ω is usually needed for fast and robust pull-down with minimum impedance.
Gate-Driver Selection
A gate-driver IC such as the TI LMG1205 is designed to handle many of the subtleties of driving GaN transistors, while still allowing the user to tailor the design for the selected device, switching speed, and other factors. The LMG1205 is optimized for use with enhancement-mode devices and can drive the high-side and low-side switches in a synchronous buck, boost, or half-bridge configuration. Independent inputs for the high-side and low-side outputs provide flexibility for designers. The driver can source up to 1.2A and sink up to 5A to prevent unwanted turn-on during transitions and features split-gate outputs to allow the current for each case to be optimized independently.
Also, to ensure high efficiency and avoid shoot through when driving high-side and low-side switches, the LMG1205 has a low propagation delay of 35ns (typical), which is matched to within 1.5ns between channels.
As well as the LMG1205, or alternatives such as the Silicon Labs Si827x series, Analog Devices ADuM4223A/B family, and Maxim MAX5048C, which are designed specifically for driving GaN devices, designers could use an existing MOSFET driver, provided it has suitable performance and features, and the switching frequency is relatively low.
In addition to choosing the most suitable driver and designing the surrounding circuitry, designers must consider all the usual issues to ensure proper switching of power semiconductors. These include optimizing circuit layout and traces to minimize stray inductances and positioning the driver as close to the transistor gate as possible to minimize external gate-to-drain coupling. A Kelvin-source connection may be needed to minimize common-source inductance, and galvanically isolating power supply rails may also be considered.
Conclusion
Commercial GaN power transistors with breakdown-voltage ratings up to 600V are now in the market, enabling power designers to take advantage of the performance gains of wide bandgap semiconductors over silicon devices such as superjunction transistors. To make the best use of the superior speed and capabilities of the new devices demands careful design of turn-on/off circuitry, including the application of high-frequency design principles to reliable switching and optimum energy efficiency.
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