Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging
Reliability is critical for integrated circuits (ICs) to ensure accurate operation over their lifetimes. However, recent advancements in semiconductors have revealed that ICs are vulnerable to reliability issues, particularly those stemming from transistor aging. Bias-temperature instability (BTI) severely affects IC reliability, degrading performance and causing critical circuit failures due to timing violations.
Additionally, asymmetric aging occurs when the degradation is unevenly distributed, intensifying timing violations and reliability concerns. This paper examines how asymmetric transistor aging affects clock tree design and highlights the role of useful skew, clock gates, and asymmetry between clock buffer delays and net delays in amplifying reliability concerns.
This paper, presented at the DVcon Europe 2023 conference, proposes new design flow guidelines to address asymmetric-aging related violations in clock trees.
Freddy Gabbay has changed his attribution and is now at the Institute of Applied Physics and Electrical Engineering, Hebrew University of Jerusalem
freddy.gabbay@mail.huji.ac.il
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