ECC Techniques for Enabling DRAM Caches with Off-Chip Tag Arrays
By
Intel Corporation
To enable a high-performance DRAM cache, previous works have proposed storing a tag array off-chip with data in DRAM. The tag-and-data access inevitably changes the traditional access pattern to memory and brings new challenges to ECC schemes due to the granularity of the data access. How to design efficient ECC for new memory usage within the restrictions of commercial DIMMs has emerged as a new challenge.
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