Flexible and Adaptive On-Chip interconnect for Tera-scale Architectures

By Intel Corporation
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Abstract: Tera-scale architectures represent a set of designs that enable high levels of parallelism to address the demands of existing and mostly emerging workloads. The on-chip interconnect element of such space is an essential ingredient with the desired flexibility and adaptivity to entertain the requirements of various designs. Highly integrated heterogeneous designs depend on a flexible interconnect topology to satisfy many different constraints. Demanding workloads create hot-spots and congestion in the network; thus, they desire an adaptive interconnect to respond gracefully to such transients. Other challenges, such as manufacturing defects, on-chip variation, and dynamic power management can also be better served through a flexible and adaptive interconnect. In this article we present the design of an on-chip interconnect with aggressive latency, bandwidth, and energy characteristics that is also flexible and adaptive. We present the design choices and policies within the constraints of an on-chip interconnect and demonstrate the effectiveness of these choices for different usage scenarios. Read More

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