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Improving Error Correction in NAND with Dominant Error Pattern Detection

Improving Error Correction in NAND with Dominant Error Pattern Detection

By Intel Corporation



This article proposes to fully utilize the error pattern characteristics abstracted from the NAND device to facilitate ECC decoding, so that we can simplify the NAND device design to reduce cost and/or improve the system’s overall reliability. We describe the ECC engine process flow. We also show decoding gains under various flipping asymmetric bits.


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