Method for Power Efficient Timing ECOs using sequential cells
On top of reduced interconnect & cell delays, the Signal Integrity effects are eating up all the uncertainty margins leaving lesser scope for downsizing cells and meeting hold timing violations. In SoC’s implemented on lower tech nodes like 28nm , around 55-60% the hold timing violations are in the paths which have no or minimal combinational logic.
Also since the Clock to flop output delays are now in range of less than the clock skew + hold time requirement , it becomes quintessential to insert hold buffers for introducing delay in the data path to meet hold timing violations in these timing paths with no or minimal combinational logic. Also current EDA tools only use the avenue of inserting buffers to fix hold timing violations or in some cases, downsizing the combinational logic instances.
Disclaimer: by clicking on this button, you accept that your data might be communicated to this company. If you do not want us to communicate your data, please update your details on your profile