At DVcon Europe 2021, engineers from Graphcore in Bristol discuss the development of a framework for modelling SoC Interconnect, chip-to-chip interconnect and other on-chip features of Graphcore’s reticle-limited 7nm Intelligence Processing Unit (IPU) Machine Intelligence Accelerator using python and the excellent SimPy package for Discrete Event Simulation (DES).
This article looks at the advantages of this purely python approach versus more traditional approaches based on SystemC or similar, with extensions to the default SimPy package that specializes it for modelling of ASIC designs. This has been applied to a framework for performance modeling and for resolving issues such as head-of-line blocking and deadlocks both prior to and after tape-out, and can be extended to clusters of many such devices.
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