TI: Using a motor driver for a low power isolated full-bridge DC-DC conversion
Introduction
There is often a requirement in an electronic system to provide an isolated voltage rail or multiple rails for powering wired interfaces such as RS485, wired mBus, 4-20mA current loops and various other types. An example application would be a smart electricity meter (eMeter). Instead of producing these rails by using additional windings on the main flyback magnetics, it is sometimes more desirable to produce these rails by taking a low voltage input and performing a low voltage isolated conversion. This avoids the main flyback converter’s magnetics from becoming too large, given the stringent safety isolation voltages and creepage and clearance rules that must be applied.
Various converter topologies are frequently used, like the flyback, fly-buck (and fly-buckboost) and the push-pull converter. This article looks at another topology – the full-bridge (or H-bridge) converter. There are a number of advantages to this topology:
- the four FETs ensure the current always has a path to flow and so there is little or no overshoot voltage spike
- it is not necessary to use a centre-tapped transformer, meaning that low-cost toroid transformers can be used having one primary and one secondary winding
- there is no energy storage and the transformer is fluxed in both positive and negative directions, which means the magnetics’ size is minimized
- integrated motor-control ICs exist that integrate the FETs and current/thermal protection. Additionally, these devices’ dv/dt edges tend to be quite slow and this benefits systems trying to avoid RF emissions which can disrupt sensitive radio receivers that are also in the system.
- Some motor drive ICs have more than one H-bridge integrated and these can be controlled separately, enabling multiple full-bridge converters to be controlled using one IC. This is useful in applications where the outputs must be independent from each other and cannot be made simply by using one transformer having multiple isolated outputs.
Design of the Full Bridge DC-DC Converter
The DRV8848 is a dual H-bridge motor control IC rated up to 18Vin which makes it ideal for 12Vin designs. Each H-bridge is comprised of high-side P-FETs and low side N-FETs. An alternative architecture is a charge pump with high-side N-FETs. The charge pump can be a source of EMI and so for this EMI sensitive application the DRV8848 is a good choice. Each H-bridge is controlled separately by AINx, BINx logic inputs and each H-bridge has a programmable current limit (CL) via using an external sense resistor (Risense) per H-bridge. When triggered, the CL reacts by turning off the FETs that were ramping up the current and then by turning on the opposite pair of FETs, making the current ramp down for 20μs (the PWM Cycle) or until the next PWM switching cycle comes along. There is also a fast internal overcurrent limit, OCP, (set to 2A min) which if triggered is followed by a hiccup retry time of 1.6ms. These protection circuits are useful for isolated converters that have to withstand a fault condition overload on their output(s). Often overlooked when making discrete FET H-bridges is the undervoltage lockout function (UVLO, ~3V in DRV8848). This prevents the FETs from switching when the supply voltage has fallen below a certain minimum level. Trying to switch the FETs on and off with a too-low supply voltage results in them entering their linear region which results in high power dissipation. The IC also generates an internal supply voltage VINT which is 3.3V ± 5%. This can be used externally, for example to power the VREF pin of the IC, so as to program the CL. Connecting VINT to VREF through an RC network ramps VREF during power-up. This ramps the CL, which gives a soft-start behaviour.
The equation for the programmable current limit (CL) on DRV8848 is VREF / (6.6 x Risense). For VREF = 3.3V then Risense = 1Ω gives a 0.5A limit.
Figure 1 shows an example schematic of the DRV8848 performing power conversion for two separately-isolated outputs. For demonstration purposes, one transformer has a centre-tapped secondary with two rectifying diodes and the other has single windings followed by a full-bridge rectifier, as this would usually be the case if the transformer is a toroid. A series 10μF capacitor was added in the primary to ensure there is never a dc offset reaching the transformer. The VREF is supplied from VINT via an RC network that fully ramps VREF in ≈10ms to implement a soft-start. The switching frequency is set to 200kHz and must be supplied externally, which can be from a microprocessor I/O pin, or it could be produced using a standalone LMC555 timer configured in 50% duty cycle mode as shown in its datasheet. DRV8848 also needs an inverted version of the clock, which is generated using an SN74LVC1G04 logic inverter gate in the schematic. To enable the IC, the nSLEEP pin must be pulled high.
A centre-tapped Coilcraft transformer (SD250-4L) with a 1:1.5:1.5 turns ratio was used for the test circuit. The second channel of the DRV8848 drives another version of the magnetics (SD250-2L) with single windings 1:1.5. The DRV8848 introduces some blanking time and this plus the rise/fall times subtracts from what would otherwise be a continuous 100% duty cycle converter. The blanking time is 200ns(typ), between the switching of the high and low side FETs in each ½ bridge. Therefore the actual duty cycle seen in Figure 2 is ~92%. The 12Vin is converted to 0.92 x 12V x 1.5 = 16.5V. The diode drop on the secondary reduces this to finally being a 16Vout output. The converter is non-regulated and this 16Vout can be expected to fall as the load increases, due to the winding resistances of the transformer, the FET on-resistances and the output inductor winding resistance. (In the case where the non-centre tapped transformer and full-bridge diode rectifier is used, then two diode drops must be subtracted). Powerstage Designer is a free downloadable TI software tool that allows you to quickly simulate the power stage waveforms for different power converter topologies. It was used to choose a suitable transformer primary inductance of 1.5mH and a smoothing secondary-side inductor of 330μH. The Volt-seconds product is calculated as Vin x ½ x T = 12V x ½ x 1 / 200kHz = 30Vμs and the selected transformer should have a Volt-seconds product that is larger than this.
Figure 2 shows the primary phase voltage waveforms. On the secondary side 16Vdc is measured. The load is 168Ω. With reference to Figure 1, when the blue phase voltage falls, it is because that phase’s high and low side diagonally-opposite FETs were turned off i.e. Q1 and Q4. There is now a dead-time period of ~200ns, during which all the FETs are off, which is integral to the IC. The leakage inductance of the transformer has stored energy and this pulls the blue phase negative and is clamped by Q2’s body diode. An oscillation starts, but very shortly after the red phase FETs Q2 and Q4 are turned on and the red phase voltage rises to 12V.
Figure 3 shows the phase voltages during start-up, where the CL is active. During start-up, VREF is ramping and the full current limit of 0.5A has not been reached. In Figure 3 the CL is ~120mA. The switching frequency has been reduced to 100kHz for this test and the load has been increased to 112Ω. (There is no particular reason why these test conditions were selected other than to show operation at a different switching frequency and load.)
The Blue phase turns on (at the first blue arrow marker) and goes high for ~1.8μs (the CL blanking time) at which point the CL has been reached and it turns off (at the second dashed-line ruler marker). The DRV8848 control logic behaviour is that the Red phase will now turn on to enable fast-decay mode, which it does so (after the second dashed-line ruler marker) and so the Red phase goes high. After about 1.6μs, the current has fallen almost to zero and the DRV8848 behaviour is that the bridge is disabled to prevent reverse current flow. There is now a period where neither phase is on, so both the phase voltages are zero. Sometime later the Red phase turns on (second red arrow) because the PWM command has gone high to turn on that phase. (This occurs before the 20μs PWM period of the IC has elapsed.) The delta between the two red arrows (or the two blue arrows) is 10μs, which is the Period of 100kHz. (The other instances where we see Blue or Red phase voltages appear are due to the CL behavior of the IC.)
It is also possible to drive the H-bridge with a duty cycle other than 92%. Figure 4a shows the INx drive waveforms for a Duty cycle of 60% and Figure 4b shows the phase voltages when driving the transformer. The leakage inductance and parasitic capacitance has time to oscillate for more cycles compared to the 92% duty cycle drive case. A better way of driving a non-50% duty cycle is to overlap the INx drive signals as shown in Figure 5a and the resulting phase voltages in Figure 5b. When both INx drive signals are high, the DRV8848 responds by turning on the low side FETs Q2 and Q4. This clamps both sides of the transformer to 0V and the result is a cleaner waveform.
Conclusion
The DRV8848 can be used to make two independent full-bridge DC-DC converters. It provides integrated protection features and is a useful addition to the techniques for generating isolated voltage rails. The fully-integrated solution for implementing two cost-effective full-bridge converters integrates protection features such as thermal limit and a programmable current limit. It also has a fast peak overcurrent limit. A soft-start can be implemented by controlling the voltage on the VREF pin. Other motor driver ICs can be used to implement a full bridge converter, ranging from low voltage devices DRV8835 / 7 / 9 to higher voltages DRV8870 / 1 / 2 and DRV8841 / 2.
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