Why ’emerging’ memories have not succeeded – yet

Why ’emerging’ memories have not succeeded – yet

Feature articles |
By Jim Handy

On July 28, seven years to the day since the initial launch of its 3D XPoint memory technology, Intel revealed that the company would “wind down” its Optane memory business.

At the time of 3D XPoint’s launch Intel called it the first new memory technology since the company introduced flash in 1988. Why is it that this technology, and so many other promising memory technologies, failed to successfully eat into the markets for established technologies?

Optane, a variant of phase-change memory (PCM) shipped in significantly higher dollar volume than did other technologies, such as FRAM, MRAM, and ReRAM, reaching annual revenues of $392 million in 2020, but in the end, it never became profitable, and that’s why Intel is exiting this business.

About the technologies

Let’s have a look at the technologies we are currently discussing. Although there are many more than these four, the leaders in maturity and market share are PCM, MRAM, FRAM, and ReRAM.  All of these are explained in much greater detail in our new report: Emerging Memories Enter Next Phase.

Of the currently-dominant memory technologies: DRAM, NAND flash, NOR flash, SRAM, and EEPROM, all except for SRAM are charge based. The SRAM is based on a flip-flop, circuit and that takes a number of transistors, usually six. While that makes the technology fast, and less sensitive to random bit flips, it also makes it significantly more costly than the other technologies which are almost exclusively based on single-transistor bit cells.

With charge-based memories they store a bit’s state as a collection of electrons on the plate of a capacitor. Oddly enough, none of the technologies below does that.  Also, every one of the technologies below is nonvolatile, yet they don’t require the enormously long write cycles typical of flash or EEPROM. They are all technically superior to established technologies and promise to scale to finer process technologies than can be supported by today’s memories.


Thanks to its use in Intel’s Optane products, phase-change memory (PCM or PRAM) has become the far-and-away revenue leader in emerging memory technologies. STMicroelectronics also produces a microcontroller (MCU) with a PCM program store, and Samsung, Micron, and Intel have all mass-produced PCM NOR flash replacements over a decade ago that had brief lifetimes.

PCM is based on a chalcogenide glass material deposited above a standard CMOS logic chip which changes its state depending on the properties of that glass. In PCM the glass changes from a crystalline state to an amorphous state to become either conductive or resistive. Intel has said that the behavior of 3D XPoint is somewhat different, but has not disclosed more than that.

PCM can be built in a crosspoint configuration where a bit can be stored at the crossing of two orthogonal conductive lines.  This lends itself to stacking, which should allow its die size and production cost to be driven below that of any established technology except for 3D NAND.

The technology has a long R&D history: Intel’s Gordon Moore co-authored an article about a 256-bit PCM prototype in 1970 with Ron Neale and D L Nelson, who were both then with Energy Conversion Devices Inc.


Magnetic RAM (MRAM) is a technology based on the physics used in all magnetic recordings (HDD, tape, etc.) but applied in a way that removes the mechanical element – nothing moves within the chip.  Everspin, spawned from research at Motorola, then Freescale, is the leader with $44 million in 2021 revenues, with Avalanche and Numem recently joining the fray. Embedded MRAM processes are available from foundries TSMC, Globalfoundries, and Samsung, and these processes are beginning to see use in SoCs designed for IoT applications and micro-power devices.

It almost seems that there are more kinds of MRAM than you can count: Toggle, STT, SOT, OST…, but they are all very similar in construction, using layers of cobalt and magnesium as a combination giant magnetoresistive (GMR) sensor and magnetic switching element. All the materials are well-understood in a semiconductor production environment, being used in high volume for HDD read/write heads.

In an MRAM, data is usually stored in a ‘free’ layer, whose magnetism can be altered, which is compared against a ‘pinned’ layer set at manufacture.  The GMR sensor detects the difference between the two.  The big difference between most MRAM variants is the way in which data is written to them. All use at least one transistor per bit cell, while many have two, and currents are rather large, rendering the technology less cost-effective to produce than others. Its key advantage is its speed. Advocates envision MRAM replacing high-speed SRAM in the future.


Ferroelectric RAM (FRAM or FeRAM) has the distinction of being the oldest emerging memory, since FRAM chips have been emerging since 1955, three years before the invention of the IC!  (Read an explanation of that sentence HERE.) FRAM technology also has the distinction of being the unit volume leader, having been included in more than four billion chips over its history.  Today Infineon produces discrete FRAM chips, while TI and Fujitsu embed the technology into MCUs. The large unit volume stems from FRAM’s use by Fujitsu in rewriteable RFID cards whose write energy is derived from the interrogating radio signal. FRAM has the lowest write energy of any of these technologies.

Despite its name, FRAM doesn’t use any iron – it simply has a hysteresis loop redolent of magnetism in iron, and that hysteresis loop allows it to store data. Physically, an atom in a piezoelectric crystal moves from one side of its molecule to the other and stays there to represent a one or a zero.

In the past FRAM has been based on either of two materials: lead-zirconate-titanate (PZT) and strontium-bismuth-tantalate (SBT), but each include elements (lead or bismuth) that worry wafer fab managers since they can easily contaminate a fab. Fortunately, in 2011 hafnium oxide (HfO) was found to exhibit ferroelectric properties under certain conditions. HfO is the basis of the high-k gate dielectrics used in FinFETs, so it’s already very well understood in a high-volume production environment, plus it doesn’t contaminate the fab. Although HfO is not used for production FRAMs today, it has a promising future.

Today’s FRAM cells have one or two transistors, limiting it to a single layer and making its die area comparable to DRAM.


Like MRAM, there are multiple variants of Resistive RAM (ReRAM or RRAM), none of which are produced by more than a single company. All are manufactured by depositing special materials over standard CMOS logic.

ReRAM foundry processes are supported by TSMC, Winbond, and Globalfoundries, and ReRAM is produced as a stand-alone product by Renesas (through the acquisition of Adesto), Fujitsu, Microchip, and Sony, and is in microcontrollers by Nuvoton. Many other companies are developing ReRAM processes.

In a resistive RAM cell current is passed between two wires to detect whether the bit cell’s resistance is high or low. Typically, the cell’s state is changed by increasing the voltage in a positive or negative direction to increase or lower the cell’s resistance, often by moving conductive elements like metal ions or oxygen vacancies into a bridge, or by removing them from an existing bridge. Purists might argue that most other technologies in this list (PCM, MRAM, and FRAM) could be grouped into the ReRAM category, since they also use a variable resistance to indicate a memory bit’s state.

One of ReRAM’s key attributes is the fact that, like PCM, it can be built into a crosspoint cell for stacking.  It is also expected to be used in neural networks since it can store linear values on a single bit cell.

Why did Optane Fail?

Optane’s failure is not because of any technical issue. All of these memories provide something of significant value, since they are all nonvolatile and consume much less energy and time to write than either NAND or NOR flash. All of them promise to reach finer process geometries than any existing memory technology, implying that they can eventually be manufactured less expensively. But this is the real problem – they have never actually come through on that promise, and in the memory business, very little matters other than cost.

Nothing makes this clearer than the dramatic transition of cell phones from NOR plus SRAM to NAND plus DRAM in 2007-2008. Both NAND and DRAM have enormously less attractive performance than NOR and SRAM, but the cost difference per gigabyte for these technologies differs by a few orders of magnitude, and that’s enough to warrant finding a work-around.

There are two factors to cost. One is die size, and the other is wafer cost. At any given process geometry many of these technologies compete against DRAM and NOR flash – SRAM doesn’t even show in a die size competition, with its 6-transistor bit-cell size. Since NAND has gone 3D, the best any competing technology can do is to copy NAND’s 3D structure to match its die size and hope to be able to match NAND’s cost, but not to outstrip it.

The second factor, wafer cost, is the one that really stands in the way of these technologies, though. If a technology runs in low volumes its wafer costs become enormously high, and that prevents the technology from gaining a foothold.  Remember, very little matters other than cost. By Objective Analysis’ estimates, any new technology must reach a wafer volume within an order of magnitude of DRAM’s to be able to match DRAM’s cost structure, even if the die size of the new technology is considerably smaller than that of the DRAM that it is trying to replace.  (This is based on the history of NAND flash cost versus DRAM cost, and how they crossed over in 2004.) 

Since DRAM volume is in the order of 18 million wafers per year, that’s a pretty big number. We understand that 3D XPoint wafer production peaked at about 0.15 million wafers per year, or at most 1/120th as many wafers as DRAM. (This paragraph includes a correction to what was first published. Thanks to David Kanter for drawing the error to our attention.)

Intel hoped to achieve high enough scale with Optane to reach this crossover, but its wafer volume was significantly below that of DRAM, and the result is evident in the chart below, which plots Objective Analysis’ estimate of Intel’s losses from the technology’s from its introduction in 2017 through 2020.  (In more recent years Intel stopped revealing enough information to estimate Optane losses.)  This chart does not include Micron’s losses from producing 3D XPoint wafers which amounted to $100-250M/quarter in late 2019 and 2020.

Estimated quarterly losses made by Intel on Optane memory. Source Objective Analysis.

So where does that leave other emerging memory technologies? 

It pretty much dictates that these technologies will never become more than niche market products.

But there’s another area that absolutely requires one or more of these emerging memory technologies.  Let’s look at that.

Potential for Success

As explained in our new report: Emerging Memories Enter Next Phase, the CMOS foundry logic used by more and more companies cannot embed NOR flash into processes smaller than 28nm unless that NOR is produced using 28nm or larger process technologies. In other words, the logic portion of the chip will continue to shrink with shrinking processes, but the NOR will remain the same size, and that will significantly slow chip cost reductions. The same appears to be the case for SRAM. At processes of about 10nm SRAM begins to scale much more slowly than logic, although it doesn’t stop altogether as does NOR.

There are four ways to deal with this for any chip with a sizeable NOR element:

  1. Continue to shrink the logic, but leave the NOR area at the same size, for slower cost reductions. This might be acceptable for chips with very little flash.
  2. Use an external NOR flash and move its contents into and out of internal SRAM caches. Although this delays the inevitable problem, it is not a long-term solution, since SRAM will also stop scaling. It is also an energy inefficient solution.
  3. Use chiplets and make the NOR flash on its own chip, using a NOR-optimized process. This will probably provide a cheaper NOR element for a while, but it will soon reach its own endpoint.
  4. Convert to an emerging memory technology, a solution that seems to have longer-term prospects than the three above. In this spirit, TSMC, Samsung, and GlobalFoundries have all introduced both MRAM and ReRAM processes to support those customers looking for such a solution.

If the fourth option catches on, it will drive wafer volume up, and higher volumes will drive costs down, rendering discrete memory chips manufactured in these foundries more fiscally attractive, which will serve to create even more volume.

So, in the end, any emerging technology that hopes to succeed will probably start life as an embedded memory in a logic process, and this will drive production costs down. These cost reductions should eventually become significant enough to allow a discrete memory chip to reach a low enough cost structure to threaten today’s leading memory technologies.

Jim Handy is founder and General Director of Objective Analysis, which provides market research and data for executives and investors in the semiconductor industry.

Related links and articles:

Emerging Memories Enter Next Phase

News articles:

Intel’s Optane memory business lost more than $500 million in 2020

Intel sells NAND memory business to SK Hynix

Samsung shows MRAM can support in-memory computing

Weebit moves ReRAM on to ‘secret-sauce’ materials

CEO interview: FMC’s Pourkeramati on roadmaps, turning away investors

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