Wide frequency universal clocks have ultra-low jitter
The design of Exar’s XR811xx synthesisers embodies a flexible delta-sigma modulator and a very wide-ranging VCO in a PLL block that has been optimised to be extremely power efficient. With a core current consumption of 20 mA, these parts dissipate 60% less power than equivalent competitive devices. The PLL can operate from either an input system clock or a crystal and incorporates both an integer divider and a high-resolution (<1 Hz) fractional divider for increased flexibility to generate any clock frequency. Up to four different frequency multiplier settings can be stored allowing for different application configurations providing BOM savings compared to multiple synthesisers. The XR811xx family also offers a choice of LVCMOS, LVDS or LVPECL output drivers.
Exar’s Universal Clock devices deliver extremely low, sub-200 fsec, output phase noise jitter as integrated over a PLL loop bandwidth of 1.875 MHz – 20MHz. This spans the requirements of most WAN and LAN systems and supports communications standards including: 10 GHz Ethernet, 2.5 GHz and 10 GHz SONET/SDH/OTN, xDSL and PCIe, as well as many other synchronised clock system applications.
The XR811xx products come in QFN10 and TSSOP8 packages as second source alternatives to existing products, for $3 to $7 depending on output options (1000).