Working group aims to standardize interoperability of multiple language verification environments and components
The mission of the MLWG is to create a standard and functional reference for interoperability of multi-language verification environments and components. Accellera is calling for participation in the newly formed group. Accellera members and the industry at large are invited to join the standardization initiative.
The MLWG will consolidate industry requirements and develop a standards-based approach to combine verification environments built in different languages. In addition, a proof-of-concept implementation is proposed to accompany the standard. The MLWG will also look at ways to enable the introduction of UVM (Universal Verification Methodology) concepts in other environments and languages that come from legacy projects. The UVM standard improves interoperability and reduces the cost of repurchasing and rewriting IP for each new project or electronic design automation tool. It also makes it easier to reuse verification components.
In addition to its own technical initiatives and working groups, Accellera supports the activities of IEEE standards including IEEE 1076 VHDL, IEEE 1666 SystemC, IEEE 1685 IP-XACT 2009, IEEE P1735 Encryption and Management of IP, IEEE 1800 SystemVerilog™, IEEE 1801 Unified Power Format (UPF) and IEEE 1850 Property Specification Language (PSL).
More about the Accellera Systems Initiative at www.accellera.org
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
