Working group looks at clock domain crossing verification issues
The Accellera Systems Initiative has formed a Proposed Working Group (PWG) to look at a standard Clock Domain Crossing (CDC) specification to ease verification of system on chip designs.
The problem comes from the fact that SoC design teams cannot reuse IP-level CDC collateral if different timing verification tools have been used for the IP blocks. This causes a clock domain verification problem when the SoC teams source IP from providers that use a different tool for their own CDC verification.
To perform holistic SoC-level verification, additional resources are needed to re-converge the IP with the verification tool used by the SoC team. Redoing this IP-level CDC verification is time consuming and hits the productivity of the design team.
Standardization on CDC collateral will bring significant benefit to not only product companies, but also IP design houses, EDA tool companies, and the entire ecosystem. The initial work will collect requirements, identify technical feasibility, identify industry interest and acceptance, and provide a recommendation to start or not start a working group.
“Currently, collateral generated from different CDC verification tools are not interoperable with each other,” said Lu Dai, Chair of Accellera. “Our Clock Domain Crossing Standardization PWG aims to address this issue. We look forward to input from the community and encourage all interested companies to join the PWG and provide guidance on the need for a standard in this area.”
“Typically, the CDC verification tools that the IP and SoC teams use rely on different formats to capture CDC intent,” said Martin Barnasconi, Accellera Technical Committee Chair. “Based on the level of interest and commitment from the community, the PWG will determine if a standard is needed to enable the interoperability of CDC collateral generated by different CDC verification tools to ease integration. If your company is interested in providing input, please join us for the initial kick-off meeting in September.”
The first Proposed Working Group meeting will be held Tuesday, September 13th from 9am – 4pm PT at Intel SC12, 3600 Juliette Lane, Santa Clara, SC12-538. Register for the meeting here. For more information about the PWG, visit here.
Participants in the PWG need not be from Accellera member companies. Companies that have already shown interest in participating in the kick-off meeting include Arm, Cadence, Intel, Qualcomm, NVIDIA, NXP, STMicroelectronics and Siemens.
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