World’s first 2D computer built in CMOS
Researchers in the US have built a complete CMOS computer out of two (2D) materials for first time, even though it runs just one instruction.
The team at Penn State used 2D molybdenum disulfide (MoS2) for the n-channel devices and tungsten diselenide (WSe2) for the p-channel to build the complementary structures one atom thick. These materials are key for building transistors with structures below 1nm in size, and the 2D implementation represents a major leap toward the realization of thinner, faster and more energy-efficient electronics, say the researchers. This follows the development of simple computers using carbon nanotubes (CNT) as well as a flexible 2D PMOS machine built with MoS2 transistors at the Technical University of Vienna. 2D materials have also recently been used for a high performance embedded memory.
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“We have demonstrated, for the first time, a CMOS computer built entirely from 2D materials, combining large area grown molybdenum disulfide and tungsten diselenide transistors,” said Saptarshi Das, the Ackley Professor of Engineering and professor of engineering science and mechanics at Penn State, who led the research.
This included a six transistor SRAM cell with pull up and pull down transistors, as well as an arithmetic logic unit. This was able to run a five stage Reverse Subtract and Skip if Borrow (RSSB) instruction using five separate one instruction set computer (OISC) structures.
Early demonstrations of silicon and non-silicon computing devices
The team used metal-organic chemical vapour deposition (MOCVD) at the 2D Crystal Consortium Materials Innovation Platform (2DCC-MIP) to grow large sheets of molybdenum disulfide and tungsten diselenide, creating over 1,000 of each type of transistor. By tuning the device fabrication and post-processing steps, they were able to adjust the threshold voltages of both n- and p-type transistors, enabling the construction of fully functional CMOS logic circuits at 3V.
“Our 2D CMOS computer operates at low-supply voltages with minimal power consumption and can perform simple logic operations at frequencies up to 25 kHz,” said Subir Ghosh, a doctoral student at Penn State.
The frequency was constrained by parasitic capacitances, along with ultra-low power consumption in the picowatt range and a switching energy down to 100 pJ.
“We also developed a computational model, calibrated using experimental data and incorporating variations between devices, to project the performance of our 2D CMOS computer and benchmark it against state-of-the-art silicon technology,” he said.
This projected the performance of the one instruction set computer and benchmarked it against state-of-the-art silicon technology using an industry-standard SPICE-compatible BSIM-BULK model.
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