World’s first 3D CMOS on CMOS stacking
French research lab CEA-Leti has described the world’s-first 3D sequential integration (3DSI) of CMOS over CMOS with advanced metal interconnect. This brings 3DSI closer to commercialization for use in the back end processing.
This is a world’s-first 3DSI demonstration of CMOS stacking with functional 3D circuits including 3D ring oscillators and a single-exposure high-dynamic-range, two-layer pixel.
Full 3DSI, in which monocrystalline CMOS devices are stacked above an industrial CMOS process, specifically when it integrates an intermediate BEOL (iBEOL) with Cu and ULK, previously has eluded researchers.
The paper at the IEDM 2023 conference in the US describes 3D Sequential Integration with CMOS stacking on 28nm industrial FDSOI with four metal layers.
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The top CMOS device process was carried out at 500°C in a 300mm fabrication on top of state-of-the art CU/ULK 28nm BEOL.
“This achievement establishes the feasibility of manufacturing high-performance silicon CMOS devices above an industrial platform, including state-of-the-art BEOL, without compromising the performance of the bottom layer. It allows reaching the full potential of 3DSI with top devices having high performance, low variability and CMOS co-integrability in contrast with BEOL transistors,” said Perrine Batude, a co-author of the paper and leader of 3DSI integration in CEA-Leti.
Additionally, the inclusion of the polysilicon ground plane “is anticipated to ensure a remarkable 40dB isolation up to 100GHz, showing a relevance of this integration for RF applications,” she said.
The paper provides a comprehensive showcase of a 3DSI platform, featuring functional 3D circuit demonstrations such as 3D inverters, 3D ring oscillators and a single-exposure high dynamic range two-layer pixel.
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