World’s first 7nm chip process for automotive
Taiwanese foundry TSMC has launched the world’s first automotive-qualified 7nm process technology.
The 7nm Automotive Design Enablement Platform (ADEP) is aimed at the development of AI Inferencing Engines, Advanced Driver-assistance Systems (ADAS) and Autonomous Driving applications, and has automotive ISO26262 and AECQ-100 qualification. The process technology will also be available for automotive product lifetimes, which are typically over 10 years.
The 7nm family of technologies has been in volume production at TMSC since 2018, which allows the company to improve the quality and yield as well as meet the rigorous durability and reliability requirements of the automotive industry.
TSMC’s ADEP is certified with the ISO 26262 standard for functional safety, and consists of Standard Cell, GPIO, and SRAM foundation IP.
This foundation IP has passed rigorous qualification according to AEC-Q100 Grade-1. Process design kits and support from third party vendor IPs are also available. Synopsys for example has LPDDR4x, MIPI CSI-2 and D-PHY, PCI Express 4.0 and security IP qualified to ISO26262 and AECQ-100 for the 7nm process.
The ADEP is based around a collaboration with EDA tool maker Ansys to boost the reliability of the 7nm process to make it suitable for automotive design. The workflows support electromigration (EM), thermal reliability including self-heat and chip package thermal co-analysis and electrostatic discharge. It also includes a new workflow for statistical electromigration budgeting (SEB).
SEB enables chip designers to meet stringent safety and reliability requirements by prioritizing the most important EM fixes for signoff while avoiding over design.
“The IPs and Systems-on-Chips (SoCs) designed for automotive applications using TSMC’s N7 (7nm) process technology offer increased integration, functionality and operating speeds but must meet rigorous requirements for functional safety and reliability,” said Suk Lee, Senior Director, Design Infrastructure Marketing Division at TSMC.
“Safety and reliability standards are increasingly stringent in next-generation automotive systems, mandating the need for a comprehensive multi-physics simulation platform that simultaneously solves for thermal effects, reliability, power-timing and performance across the spectrum of chip, package and system,” said John Lee, General Manager at ANSYS.
The 7nm process workflows are based on the Ansys RedHawk power integrity and reliability sign-off tool, RedHawk-CTA integrated chip–package co-analysis and co-visualization tool and Totem, a transistor level power integrity and reliability signoff solution for full-custom/analogue and mixed-signal designs. In addition to static IR and dynamic voltage drop analysis, Totem can include the substrate network, along with package and board models, for chip-package-system co-analysis. Totem can also perform thermal-aware power and signal line electromigration analyses.
Another tool, called PathFinder, helps users plan, verify and sign-off IP and full-chip SoC designs for integrity and robustness against ESD. The analysis is performed at the layout and circuit levels to help user identify and isolate design issues that can cause chip or IP failure from charged-device model, human body model or other ESD events.
“Automotive applications have always demanded the highest level of quality. With the advent of ADAS and autonomous driving, powerful and efficient computing is now also required to enable AI inferencing engines to perceive the road and understand traffic to help drivers make split-second decisions,” said Dr. Cliff Hou, Senior Vice President of Research & Development and Technology Development at TSMC. “TSMC is uniquely positioned with our 7nm experience and comprehensive design ecosystem to unleash our customers’ innovations and achieve first-time silicon success while meeting the rigorous demands of bringing safer and smarter vehicles to market.”
TSMC’s fabs are certified with IATF 16949 for automotive product manufacturing, and TSMC also provides an Automotive Service Package for wafer manufacturing. This has tighter controls and enhanced gating compared to the consumer 7nm process to achieve automotive PPM reliability, as well as a Safe Launch Program during production ramp to ensure the success of new product introduction.