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World’s first native plastic programmable processor

Technology News |
By Nick Flaherty

UK plastic chip maker PragmatIC Semiconductor has worked with researchers in the US on the first programmable processor designed specifically for a plastic process technology.

PragmatIC and its partners have previously demonstrated the world’s first non-silicon ARM processor and also designed the iconic 6502 processor for its flexible plastic technology, but this is the first project to explore the performance, power, size and yield trade-offs of the technology.

This is the first time that a microprocessor has been developed specifically for PragmatIC’s FlexIC Foundry service, using bespoke chip architectures designed by researchers at the University of Illinois.

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The research team, led by Rakesh Kumar, Professor in the Electrical and Computer Engineering Department at the University of Illinois, developed an optimised semiconductor architecture that successfully delivered a functional yield of 80% per wafer on PragmatIC’s commercial process for flexible integrated circuits.

The team designed, fabricated and tested hundreds of cores built in a flexible 0.8 µm IGZO TFT-based field-reprogrammable 4 and 8-bit microprocessor chips optimized for low footprint and yield.

The research showed that the optimized processors can have high yield of 81%, sufficient to enable sub-cent cost if produced at volume. These have also been characterised for the first time.

The paper is here: PragmatIC_FlexiCore4_native _plastic_processor

The FlexLogIC chip making process supports IGZO circuits made using n-type TFTs with resistive pull-up. The circuits are manufactured on a 30 µm flexible polyimide substrate which enables the TFTs to flex up to a radius of curvature of 3 mm without damage. This can be used in medical patches or many sensor designs.

To fabricate IGZO integrated circuits, FlexLogIC uses a proprietary manufacturing process that deposits layers of IGZO TFTs and resistors and four routable aurum-free metal layers onto a 200 mm wafer of polyimide which has been spin-coated onto a glass backing. After fabrication, the flexible polyimide wafer can be removed from the glass backing.

However the n-type logic-based 0.8 µm IGZO devices have poor noise margin, high power consumption, and significant variation in threshold voltage (𝑉𝑡ℎ), which lead to yield and energy efficiency concerns.

Almost all (99%) of the power consumption is static power, which requires power reduction to be achieved primarily through area reduction, and this led to a size limit of 800 NAND gates and constraints on the Instruction Set Architecture (ISA) that could be used.

For comparison, the area of the flip-flops in an ARMv6-m machine’s register file is more than three times this allowable area. The on-chip data memory of the smallest PIC MCU (PIC10F200) is 704 NAND2 equivalent area, 88% of the area limit and the architectural registers of the Intel 4004  have the area of 638 NAND2 gates.

The 4bit FlexiCore4 supports a four-bit datapath as this is adequate for many target applications, with a seven-bit program counter, a four-bit accumulator register, an eight-word (four octet) integrated data memory, and three arithmetic and logical functions (ADD, NAND, and XOR).

The team also developed an 8-bit version, called FlexiCore8. Since doubling the size of the internal data[ memory was area prohibitive given the 800 NAND2-equivalent area restriction, they instead halved the number of words in memory, while doubling the width from a nibble to an octet. FlexiCore8 adds an additional LOAD BYTE instruction, which loads an 8-bit immediate value into the accumulator.

Programs are written in a highly readable assembly language and assembled into machine code binaries by a custom assembler written in Python. Some of the programs require more than 128 instructions (e.g., Calculator, Decision Tree) and to execute these, the team used an off-chip memory management
unit (MMU) driven by FlexiCore’s output port. The MMU allows extending the program memory address space beyond the 128 instructions enabled by the 7 bit program counter alone.

The MMU consists of finite-state transducer based controller, and a four-bit register. When the controller identifies a specific sequence of values on the FlexiCore’s output port, it stores the value of
the output port into the register after a short delay. This allows software to signal a ‘page change’ to one of sixteen different 128-instruction pages, and then branch to a desired location within that page. This technique can be extended to support arbitrary number of pages

The cores were tested with a suite of representative kernels at 12.5kHz that took 4.28 ms to 12.9 ms and 21.0 µJ to 61.4 µJ for execution (at 360 nJ per instruction).

After synthesis and place and route, the FlexiCore4 and FlexiCore8 have area of 5.56 mm2 and 6.06 mm2 respectively and static power of 1.8 mW and 2.4 mW respectively.

For comparison, they also synthesized a small, conventional silicon microcontroller, the TI MSP430, using the openMSP430 RTL. In 0.8 µm IGZO, this core has an area of 170 mm2 , 30 times larger than FlexiCore4. The MSP430 also consumes 41.2 mW static power, 23 times more than FlexiCore4.

This work highlights the design optimisation with flexible integrated circuits and characterised the yield of the different designs.

“Because PragmatIC’s tapeout cost is orders of magnitude below conventional silicon and its production cycle time is extremely fast, it allows designers to quickly and cost effectively develop new semiconductor hardware products and improve them with each iteration,” said Scott White, CEO of PragmatIC.

This enables agile design that is today only possible with software. While a conventional silicon a tapeout cycle could take as long as six months (and is currently closer to 18 months due to global supply chain issues), the PragmatIC technology takes a few weeks. This means that rather than overengineering to accommodate every possible future use, designers can efficiently develop made-for-purpose ICs.

The project demonstrates for the first time that designs can be efficiently optimised around the specific characteristics of the technology platform, leading to products that have the best balance of functionality and performance against cost and other target parameters. The paper illustrates this in the context of microprocessors, showing significant optimisation of footprint, cost, yield, and power consumption.

Design space exploration identified design points much better than FlexiCores for new cores that  consume only 45-56% the energy of the base design, and have code size less than 30% of the base design, with an area overhead of 9-37%.

“While our customers have the opportunity to use off-the-shelf or industry-standard designs and IP cores, as demonstrated with PlasticArm and the Flex6502, the full potential of PragmatIC’s technology can be unlocked by design innovation that exploits its unique characteristics to deliver novel flexible ICs that can be used to embed electronics in trillions of everyday items,” he said.

www.pragmaticsemi.com

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