World’s first Software Defined Baseband chip for LTE-Advanced
The device is supplied in a system-level development platform providing support for rapid development, debug and validation, against reference test equipment such as the R&S series of communications testers, or integration with RF devices for field testing
“Creating a chip was the logical next step for us, allowing us to showcase the performance of our core IP, and at the same time providing a validation platform for our customers whilst their own chips are under development,” said Dr Gordon Aspin, CEO at Cognovo. “The benefits of the soft modem approach are clear: the silicon came back around 5 weeks ago and we have already brought up a Cat4 LTE downlink. The device is dimensioned for future standards supporting in excess of 300 Mb/s. By using this device our customers can develop soft modems, ranging from 2G to beyond 4G, all on the same silicon.”
Cognovo’s soft modem approach uses a cluster of high performance Vector processors programmed in high level C code, together with a novel control and scheduling system. Because the generic hardware is configured by software alone, the hardware can be finalised before the software, and the same chips can be used in development and the final product. The CDC160 device can also be used to support development of other modem standards, such as LTE, 3G, or 802.111abg, n, af, ac etc.
Cognovo has instantiated its IP core in a baseband device to provide customers with a development vehicle and to prove the performance of the IP.
As the next generation 4G wireless broadband standard defined in 3GPP, LTE-Advanced is capable of supporting data rates in excess of 1Gb/s, or three times the performance of the 3.9G systems rolling out today. Developing new wireless modems in software directly on target silicon allows manufacturers to save cost and time, as well as de-risk the complex modem development process.
“A key requirement for any modem solution is die size and power consumption and we have worked hard to benchmark our solution against existing approaches. Even though the device can offer up to 250 GOp/s, I am pleased to report that the power consumption is on-par with the best dedicated ASIC designs and the die size is smaller,” said Aspin.
Cognovo’s SDM Development Environment allows efficient power/performance implementation of the complex mathematics that underlies advanced wireless modems, and enables the overall system design to be defined in diagrammatic form and compiled directly to run on the hardware. This approach makes the power of the chip available to existing modem development engineers in a form with which they are familiar, ensuring that their design can move smoothly from laboratory development to product launch.
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