
World’s first UCIe heterogeneous chiplet test chip
Synopsys and Intel have developed the first test chip with the Universal Chiplet Interconnect Express (UCIe) protocol used to connect chiplets made on different processes.
The test chip demonstrated UCIe traffic between Synopsys UCIe PHY IP and Intel UCIe PHY IP, simulating each test chip using the Synopsys VCS functional verification tool.
Intel’s test chip, Pike Creek, consists of an Intel UCIe IP chiplet fabricated on Intel 3 technology and was paired with a Synopsys UCIe IP test chip fabricated on the TSMC N3 process. The successful pairing mimics the mixing and matching of dies that can occur in real-world multi-die systems, demonstrating that this approach is commercially viable.
The combination of devices built on different process technologies is key for boosting the complexity of system in a single package using the UCIe protocol.
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The collaboration uncovered some lessons learned that they plan to share with the UCIe Consortium says Manuel Mota, senior staff product manager for high-speed interface IP for the Synopsys Solutions Group.
As silicon manufacturing takes a long time, and validating that everything works as intended is also cost- and time-intensive, finding a way to use existing test chips or silicon can be a good way to assess compatibility.
Designing multi-die systems involves extensive planning, especially if for re-use of the package or board designs. Building in as much flexibility as possible in the boards is one way to provide options for future use.
An open standard like UCIe provides confidence of interoperability. When one company controls both sides of a link, there are, of course, no concerns about whether each side will work together. But moving forward, over the next few years, he expects to see more companies who prefer not to build both sides, instead choosing to buy components off the market which could well be made on different technologies. This was highlighted at the recent DVcon Europe panel on chiplets.
- DVcon Europe looks to open source EDA challenges
- Winbond to support chiplet interface standardisation
- €16m project to secure the chiplet supply chain in Europe
By allowing partitioning of a design to include multiple process nodes, chiplets help to mitigate the expense of manufacturing at advanced nodes. Without a standard, IP availability is limited, and choosing a process node based on IP availability isn’t an optimal approach, says Mota. The UCIe test chip interoperability demo provides a solid proof point for mixing and matching IP designs and lays the foundation for an open chiplet ecosystem.
One of the advantages of a multi-die system architecture is that it can consist of dies from different vendors for different process nodes. This provides flexibility in terms of cost and in optimizing power, performance, and area (PPA). UCIe is a key ingredient to bring the disparate components together, enabling them to communicate with one another while supporting a range of advanced packaging technologies.
While a UCIe-compliant multi-die system may work well through development, testing, and manufacturing, the project needs to ensure that the system’s die-to-die connectivity will remain reliable from the start and in the field. This is where UCIe IP plays an integral role.
UCIe IP typically consists of a controller for low latency between dies based on common protocols, such as PCIe, CXS, and Streaming protocols; a PHY for high-performance and low-power connectivity in a package; and verification IP to accelerate verification closure. Built-in testability features enable you to root out defective dies at the naked die testing phase. In addition to these testability features for known good dies, the IP can also provide cyclic redundancy checks (CRC) or parity checks for error detection and retry functionality for correction of detected errors.
Intel says it plans to continue collaborating with Synopsys as it further develops its UCIe technology and close collaboration across the semiconductor ecosystem will be essential in enabling chip designers to realize the benefits of these complex, interdependent designs.
www.synopsys.com; www.intel.com
