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X-Silicon fuses GPU with RISC-V vector CPU in single AI core

X-Silicon fuses GPU with RISC-V vector CPU in single AI core

Technology News |
By Nick Flaherty



San Diego startup X-silicon has developed an IP core that combines a RISC-V processor with open standard Vulkan GPU for AI and machine learning chips.

The NanoTile  “C-GPU” architecture developed by X-Silicon adds GPU acceleration into a RISC-V Vector CPU Core with tightly coupled memory for a monolithic processor core that runs the Vulkan open graphics standard.

The C-GPU is offered as IP blocks and software for processor companies to develop low-power SoCs for next generation 3D graphics, compute, and AI/ML enabled wearables, AR/VR headsets, auto displays, edge and cloud processing, industrial systems, robotics, and other connected embedded/IoT devices.

The company is already working on chip designs using the IP with SiFive and Ventana Micro Systems. Ventana already uses GPU cores from Imagination Technologies in the UK for its RISC-V AI chiplet designs.

X-Silicon says it will open-source its unified RISC-V Vector CPU-with-GPU Instruction Set Architecture (ISA) and provide register-level access to its hardware via a Hardware Abstraction Layer (HAL). This strategy is aimed at the customers for the chips, allowing OEMs and content providers to customize their drivers and applications to a greater level than is currently possible.

X-Silicon is also the first to offer Vulkan on RISC-V with fused GPU acceleration, making it suitable for Android devices.

Rather than using triangles to render graphics, the X-Silicon C-GPU is designed from the ground up to optimally render and manage dynamic content using a single C-GPU processor with multiple NanoTiles. This architecture is more suited to implementing more efficient graphics, AI and compute algorithms without being bound by the limitations of today’s GPUs says the company.

The NanoTile architecture is supported by 14 patents covering AI/ML Compute and GPU rendering using a single processor. The key claims deal with ways in which data is shuttled among the processing cores and memory, reducing latencies, and improving compute efficiency. The patented IP also enables the NanoTile architecture to be deployed within edge and cloud configurations, enabling a federated model for GPU compute.

X-Silicon C-GPU architecture

Multiple C-GPU cores are tiled across a chip and connected using an on-chip fast compositor fabric that can dynamically aggregate outputs from each core into a common buffer. This can be a frame buffer for graphics or pipelined buffers for codec, video effects processing, and AI processing, and each core can be software-programmed for different workloads.

This allows fast on-chip SRAM or eDRAM to serve as Level 2 caches that can aggregate the data from multiple cores. In memory compute with common operations done close to memory, will further reduce bandwidth and further increase performance.

Workloads can be implemented in parallel or pipelined, and run simultaneously on a core as opposed to sequentially on traditional GPUs. It can also run an operating system on a core.

“We want to enable enhanced visual experiences directly on industrial and consumer devices where users have become accustomed to using their mobile phone displays for UI, while enhancing the intelligence on these edge devices. We also want to enable low power visual computing in the cloud that supports novel methods, leapfrogging the capabilities that are available with closed systems. Our Open-Standard, Patented C-GPU Nano Tile architecture is ideally suited for processor companies targeting SoC solutions for low-power markets,” said Dan Nilsson, CEO of X-Silicon.

“By providing register level access through a Hardware Abstraction Layer, we not only enable novel and more efficient methods for rendering but also ensure compatibility across multiple hardware generations – a feature highly desired by consumer, industrial IoT and automotive OEMs with longer product life cycles.”

“For over twenty years, the industry has been seeking an open-standard GPU flexible and scalable enough to support a variety of markets such as AR/VR, automotive, connected IoT and the vast embedded verticals including robotics,” said analyst Jon Peddie. “I am intrigued by X-Silicon’s dynamic and highly scalable C-GPU Nano Tile architecture and its capability to handle multiple tasks simultaneously or sequentially, including OS, applications, graphics, compute and AI/ML processing. They are unique in this regard.”

“We are pleased to work with X-Silicon as they bring their Vulkan-enabled graphics rendering solution for the RISC- V ecosystem and add exciting 3D graphics to the edge platforms that cannot access other proprietary GPUs available in the market,” said John Runco, Senior Vice President of Product at SiFive. 

“X-Silicon’s solution enables these platforms to offer enhanced UI capabilities with a single high-performance RISC-V processor. We look forward to working together to bring new graphics capabilities to consumer & embedded customers with X-Silicon’s RISC-V-based Open-Standard Vulkan-Enabled implementation.” 

“Ventana Micro Systems is excited to partner with X-Silicon as a key graphics and compute solution provider within the RISC-V ecosystem. X-Silicon’s innovative software-accelerated graphics and compute solution aligns seamlessly with RISC-V’s vector capabilities, showcasing a powerful combination that enhances the performance and efficiency of edge computing solutions,” said Balaji Baktha, Founder & CEO of Ventana Micro Systems.

“By combining X-Silicon’s Open-Standard Vulkan-enabled GPU architecture with our high-performance RISC-V CPUs, we seek to enable new and versatile applications for edge computing and data centres,” he said.

The company plans to make its software development kits available to a select set of early development partners later this year.

www.x-silicon.com

 

 

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