
Xilinx’ 20nm All Programmable UltraScale portfolio shipping now: plans for 4.4M logic cell device
14.00
The UltraScale devices are said to deliver a 1.5x to 2x increase in system performance and integration while consuming up to half the power, relative to currently available solutions.
Part of their new UltraScale architecture, the FPGAs feature ASIC-like clocking with local clock domains that can be flexibly placed, and enhancements to the logic and fabric to eliminate interconnect bottlenecks. The chips are designed to support consistent device utilization of more than 90% without performance degradation.
The new Kintex UltraScale FPGAs deliver up to 1.16M logic cells, 5,520 optimized DSP slices, 76 Mbits of BRAM, and 16.3Gbps backplane-capable transceivers. They also feature PCIe Gen3 hard blocks, integrated 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP Cores, and DDR4 memory interfaces.
The largest family member in the new Virtex UltraScale family of devices will be the XCVU440, delivering 4.4M logic cells, 1,456 user I/Os, 48×16.3 Gb/s backplane-capable transceivers and 89 Mbits of Block RAM.
Effectively, it will more than double Xilinx’s industry’s highest capacity Virtex-7 2000T device, delivering 50M equivalent ASIC gates for next generation production and prototyping applications.
Currently, Virtex UltraScale devices include 28Gb/s backplane-capable and 33Gb/s chip-to-optics transceivers, in addition to integrated PCIe Gen3, 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP cores, and DDR4 memory interfaces to support multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates.
The company will offer a number of packaging options with footprint compatibility between the Kintex and Virtex UltraScale families, enabling designers to secure a simple migration path to scale up their designs.
UltraScale devices are supported in the Vivado Design Suite 2013.4 release and full product documentation is now available at www.xilinx.com/kintex-ultrascale and www.xilinx.com/virtex-ultrascale.
Visit Xilinx at www.xilinx.com
Normal
0
false
false
false
EN-IE
X-NONE
X-NONE
/* Style Definitions */
table.MsoNormalTable
{mso-style-name:”Table Normal”;
mso-tstyle-rowband-size:0;
mso-tstyle-colband-size:0;
mso-style-noshow:yes;
mso-style-priority:99;
mso-style-parent:””;
mso-padding-alt:0cm 5.4pt 0cm 5.4pt;
mso-para-margin-top:0cm;
mso-para-margin-right:0cm;
mso-para-margin-bottom:10.0pt;
mso-para-margin-left:0cm;
line-height:115%;
mso-pagination:widow-orphan;
font-size:11.0pt;
font-family:”Calibri”,”sans-serif”;
mso-ascii-font-family:Calibri;
mso-ascii-theme-font:minor-latin;
mso-hansi-font-family:Calibri;
mso-hansi-theme-font:minor-latin;
mso-ansi-language:EN-US;
mso-fareast-language:EN-US;}
