Xilinx adds HBM2e fast memory to FPGA
Xilinx has added HBM2e high bandwidth memory chips to its high end 7nm Versal FPGAs
An HBM2e controller and 32 port network switch has been added to the chiplets that sit on top of the FPGA fabric to interface to one or two HBM2e chips in the Versal HBM package. This provides up to 820Gbyte/s bandwidth to 32Gbytes of memory linked to the Versal FPGA chip.
Xilinx uses commercial memory chips with 1024bit wide interfaces from all three HBM suppliers for memory bound applications for data centre, wired networking, test and measurement, and aerospace and defence.
“The HBM2e components we source from multiple vendors but the controller and switch is our own IP,” said Mike Thompson, Senior Product Line Manager for Versal Premium and HBM ACAPs
The HBM2e chips are themselves stacks of memory die. The 8GB version uses a single stack with dummy slug for coplanarity and cooling, while the 16 and 32GB versions use two stacks.
The ACAP chips use CoWoS 3D chip assembly that is available from multiple packaging houses, says Thompson.
Having the memory controllers and PCIe interface on the chiplets allows the iterfac and memory to wake up in under 100ms to move data around while the rest of the device is configuring from the bitstream, he says. The other chiplets on the versal HBM include a mix of PAM4 and NRZ transceivers and ARM Cortex A72 processor cores and R5F real time controller cores.
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“Many real-time, high-performance applications are critically bottlenecked by memory bandwidth and operate at the edge of their power and thermal limits,” said Sumit Shah, senior director, Product Management and Marketing at Xilinx. “The Versal HBM series eliminates those bottlenecks to provide our customers with a solution that delivers significantly higher performance and reduced system power, latency, form factor, and total cost of ownership for data center and network operators.”
The chiplets in the package provide 5.6Tb/s of serial bandwidth with 112Gb/s PAM4 transceivers, 2.4Tb/s of scalable Ethernet bandwidth, 1.2Tb/s of line rate encryption throughput, 600Gb/s of Interlaken connectivity, and 1.5Tb/s of PCIe Gen5 bandwidth with built-in DMA, supporting both CCIX and CXL.
The Versal adaptive compute acceleration platform (ACAP) FPGA includes adaptable engines for low-latency hardware parallelism, DSP engines for AI inference and signal processing, and scalar engines for embedded compute, platform management, and secure boot and configuration. The Versal HBM series can dynamically reconfigure hardware in milliseconds to adapt with evolving algorithms and emerging protocols, eliminating the need for hardware redesign and re-deployment.
The Versal HBM ACAPs deliver network scalability and performance for 800G routers, switches, and security appliances rathe than using a traditional network processing unit (NPU) implementation that would require multiple NPU devices and DDR modules
The ACAP devices can be programmed by either hardware and software developer using the Vivado Design Suite for hardware, the Vitis unified software platform and Vitis AI for data scientists with domain-specific frameworks and acceleration libraries.
Developers can start prototyping on existing Versal Premium series devices and evaluation boards and readily migrate to the Versal HBM series that will begin sampling in the first half of 2022. Documentation is available now and tools will be available in the second half of 2021 via an early access program.
Related Versal article
- Customer Shipments of Versal ACAP
- Xilinx, Mavenir team for Open RAN Massive MIMO
- Adaptable platform targets network and cloud acceleration
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