Xilinx and Avnet partner to launch TSN evaluation kit
When Xerox PARC developed Ethernet in the 1970s, the focus was on connectivity; latency or throughput were not the most important factors in the 3 Mbit/s network technology of the time. At the few network nodes there were people sitting with workstations and laser printers, and nobody was bothered if the data packets occasionally collided during transfer and had to be transferred several times. The joint transmission of long and short packets resulted in certain delays for the shorter packets as they had to wait for the priority transfer of the longer packets.
Today, Ethernet is the most widely used wired data transmission technology, and the application landscape has expanded enormously. Transmission speeds have multiplied. This significantly increases capacity, but does little in terms of latency or bandwidth optimization. Packets are still suppressed under high network load and must be transmitted repeatedly.
In response to this limitation of the usefulness of Ethernet in applications that require precise and deterministic timing, the IEEE 802 Committee responsible for Ethernet specifications has created a set of new substandards known as Time Sensitive Networking (TSN), which allow different classes of traffic on a common link and guarantee its synchronization in terms of latency and quality of service.
However, the appropriate implementation of TSN is still a major technical challenge. In classical Ethernet, when a network node sends a data packet “A”, it must complete its transmission before sending another data packet. It becomes difficult when another, but more urgent, packet “B” suddenly moves to the top of the queue, because otherwise it would miss a deadline. The sender must wait for the transmission of packet A to complete – or abort it, send packet B first, and then resend the entire packet A. The sender must then wait for packet “B” to complete its transmission. The (undesirable) result: The effective bandwidth is limited to minimize latency.
In TSN-enabled networks, however, the sending node can effectively pause packet A during transmission, transmit packet B first, and then continue with packet A where it interrupted it. Even with relatively slow networks (100 Mb/s), the controller has less than 82 µs to evaluate all queuing options and decide how best to proceed. At gigabit speeds, this time window is reduced to 8 µs.
The implementation of TSN thus requires a combination of microprocessors and the specific decision making capabilities of FPGAs. Xilinx is therefore working closely with two groups involved in this process – the AVnu Alliance and the Industrial Internet Consortium – who have been working on TSN for several years. Xilinx already demonstrated key industrial protocols such as OPC UA, DDS and EtherCAT based on TSN at SPS IPC Drives 2016 in Nuremberg, Germany.
In 2017, Xilinx released a preliminary version of its own TSN support under the title “1G/100M TSN Subsystem LogiCORE IP”. It works with the Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC devices and provides single-chip solutions for a variety of applications. At SPS IPC Drives 2018, Xilinx demonstrated a MARA Collaborative Robot (Cobot) from Acutronic Robotics that critically depends on real-time control of its speed, accuracy and safety. Xilinx’s Zynq-based TSN solution enables Ethernet-based communication as used in multi-axis cobots.
Other customers with early access to Xilinx products have also achieved promising results. General Electric, for example, comments: “In our internal testing, the Xilinx IP core has met some of our most stringent requirements. In terms of performance, we measured a variation in packet delay of less than 50 ns (peak-to-peak). We found that the Xilinx IP core extensively met TSN specifications. Because of the IP core flexibility, Xilinx was able to further improve this performance as the standards matured and add additional functionality that is very much in line with the development of our product and its lifetime.”
In total, since the announcement of the 1G/100M TSN subsystem LogiCORE IP, several dozen customers have purchased licenses to integrate the Xilinx TSN IP into their products. To help developers get their TSN projects off the ground, Xilinx is collaborating with Avnet to market a TSN Evaluation Kit (AES-ZU-TSN-SK-G). It is available until December 31, 2018 at a special introductory price of $10,000. From 2019, the price of the kit will be increased back to the normal $27,000. The kit includes two hardware TSN nodes developed by Avnet with a total of six boards, and a full project license that allows the user to use the Xilinx TSN Endpoint IP on Zynq or Zynq UltraScale+ SoCs in production.
Computing power requirements for Time Sensitive Networking are rather high. But the real-time constraints prevent simple solutions based on standard microprocessors, and the rapidly advancing standards make custom ASIC solutions quite complicated. These are the application types for which these products were developed at Xilinx. The recognition from Xilinx customers shows the intrinsic value of this approach and it is expected that it will solve even greater challenges in the future.
More information: www.xilinx.com
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