Xilinx confirms product plans at 20nm: previews 4.4M logic cell FPGA
The programmable device company is describing its 20nm all-programmable UltraScale portfolio as having “ASIC-class Architecture and ASIC-strength Design Solution” to indicate that it believes it has the density to displace some of the largest ASIC designs previously beyond the reach of programmables: and that its Vivado tool chain offers a very “ASIC-like” route to completing large designs.
Xilinx says it shipped its first 20nm silicon in early November 2013. UltraScale devices enable 1.5x to 2x “realisable” system performance and integration, and consume up to half the power, relative to currently available solutions. These devices use advanced routing, ASIC-like clocking, and enhancements to logic and fabric to eliminate interconnect bottlenecks while supporting a claimed, consistent, device utilsation of more than 90% without performance degradation.
The Kintex UltraScale FPGAs contain up to 1.16 million logic cells, 5,520 optimised DSP slices, 76 Mbits of BRAM, 16.3 Gbps backplane-capable transceivers, PCIe Gen3 hard blocks, integrated 100 Gb/sec Ethernet MAC and 150 Gb/sec Interlaken IP Cores, and DDR4 memory interfaces. Xilinx indicates it expects typical application profiles will be represented by 8K/4K super high resolution displays and equipment; 256-channel ultrasound; 8X8 mixed mode LTE and WCDMA radio with smart beamforming; 100G traffic management/NIC; and DOCSIS 3.1 CMTS equipment.
Virtex UltraScale devices will range up to 4.4M logic cells, 1,456 user I/Os, 48 x 16.3 Gb/s backplane-capable transceivers and 89 Mbits of Block RAM, breaking previous records by more than doubling Xilinx’s industry’s highest capacity Virtex-7 2000T device and delivering 50M equivalent ASIC gates. This will be “3D” device (often termed 2.5D because it comprises separate dice laid side-by-side on a connecting interposer) with three slices. Virtex UltraScale devices include 28 Gb/sec backplane-capable and chip-to-optics transceivers uprated to 33 Gb/sec, in addition to integrated PCIe Gen3, 100 Gb/sec Ethernet MAC and 150 Gb/sec Interlaken IP cores, and DDR4 memory interfaces to support multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates. An applications list forn then Virtex devices might comprise; single chip 400G MuxSAR; 400G transponder; 400G MAC-to-Interlaken bridge; and, as with the largest devices in every FPGA generation, emulation and prototyping.
That largest device, coded Virtex UltraScale VU440, will deliver, the company says, more at 20nm than publicly stated competitive plans at 14/16nm. Xilinx will not be drawn on the likely cost of the part, but the inference is that it will be several tens of thousand of dollars each. Xilinx says that the scalability of the Virtex UltraScale VU440 device is made possible by its ASIC-class architecture – for up to 90% utilisation featuring next generation routing, ASIC-like clocking, power management, elimination of interconnect bottlenecks, and critical path optimisations. Detail changes include a more ASIC-like clock dsitribution scheme, to reduce skew between clocks feeding physically separated functions. Along with major advancements to key architectural blocks—such as wider multipliers, high speed memory cascading, 33G capable transceivers, and the addition of integrated 100 Gb/sec Ethernet MAC and 150 Gb/sec Interlaken IP cores, these devices enable multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates.
The 2.5-D structures use TSMC’s CoWoS manufacturing technology; this generation of SSI technology features 5x more inter-die bandwidth and a unified clocking architecture across slice boundaries to deliver a “virtual monolithic design experience”. Xilinx says its SSI technology enables Xilinx to deliver devices with 2-4x the capacity of competing devices and continue to stay ahead of what Moore’s Law could otherwise offer.
Xilinx UltraScale devices are supported in the Vivado Design Suite 2013.4 release and full product documentation is now available at www.xilinx.com/virtex-ultrascale
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