Xilinx preps programmable RF for 5G

Xilinx preps programmable RF for 5G

Technology News |
By Peter Clarke

Typical applications are massive MIMO for 5G and millimeter wave wireless backhaul, although the general approach of adding high frequency analog in leading-edge digital processes could have wider implications for Xilinx’s evolution. The first products in the RFSOC range are expected to start shipping in 2H17.

As a vendor of FPGAs Xilinx has long-held a prominent position selling its chips for basestations and remote radio heads and the inclusion of RF analog on its silicon is an extension of that position, said Kirk Saban, product manager for FPGAs and SoCs at Xilinx.

The RFSOC family of products will be based on the Zynq UltraScale+ family of MPSOCs, which are implemented in 16nm FinFET digital CMOS process. These devices include up to four Cortex-A53 cores, the option of dual-core Cortex-R5 real-time processors, as well as different-sized areas of programmable logic. The family comes with numerous high-speed interfaces to memory.

Xilinx is adding multi-gigasample RF ADCs and DACs and a signal train for digital signal conditioning in both the up and down directions at radio frequency. This eliminates the need for external ADCs and DACs and enable the chip to connect directly to RF power amplifiers and low-noise amplifiers on the send and receive sides. It also allows scalability for multi-element phased-array antennas.

The 16nm-based RF data conversion is much more aggressive than is available in stand-alone components and includes: direct RF sampling for simplified analog design, greater accuracy, smaller form factor, and lower power. These include sets of 12-bit ADCs at up to 4GSPS, high channel count, with digital down-conversion and 14-bit DACs at up to 6.4GSPS, high channel count, with digital up conversion.

Next: Eliminate the JESD204

As well as sweeping up the ADCs and DACs this architecture elimates the need for JESD204 interfaces and high-speed SERDES communications. For 4 x 4 to 8 x 8 MIMO architectures total power savings range from 13W to 28W and from 41 to 51 percent of an FPGA-plus-discrete architecture.

“The shift to FinFET technology blends high integration density with improvements in analog device performance characteristics,” said Boris Murmann, Professor of Electrical Engineering at Stanford University, in a statement issued by Xilinx. “This enables the integration of leading-edge analog/RF macros using a digitally assisted analog design approach.”

Saban of Xilinx said product details and datasheets for the RFSOC range would follow and products ship in 2H17. He added that Xilinx also has a roadmap to take such RFSOCs down to 7nm. In addition the same strategic approach could be taken in other application areas such as DOCSIS for cable heads and for aerospace and military radar applications.

The development team for this technology is based in Dubln, Ireland, and has been working on the technology for several years.

Related links and articles:

Xilinx white paper

News articles:

GloFo 45nm RFSOI process ready for 5G

Xilinx expands ecosystem around Zync MPSOC

SoC module is built on the Xilinx Zynq UltraScale+ MPSoC

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